DESIGN METHOD AND DESIGN APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT

• US 20090019412A1
• Filed: 07/10/2008
• Published: 01/15/2009
• Est. Priority Date: 07/10/2007
• Status: Abandoned Application

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Kyoya, Muneaki, Nakanishi, Ryo, Shiokawa, Tetsuji, Yoshimura, Masahiro, Iijima, Noriko, Nishioka, Satoru
• Application Number:
  US12/170,538
• Publication Number:
  US 20090019412A1
• Time in Patent Office: Days
• US Class Current: 716/119
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

According to the present invention, timing information, connection information and physical information are received, and at the weighting determination step, the degree to which a cell can move is weighted. Then, at the movement range determination step, the movement enabled range of the cell is determined, and whether or not a cell placement area is available is decided. When it is decided that a cell placement area is available, the processing advances either to the cell movement area extension step or to the cell placement area acquisition step. Thereafter, an automatic, optimal placement process is performed for the cell.

Claims

1. A design method for a semiconductor integrated circuit comprising:

a first weight determination step of first receiving timing information and connection information (hereinafter referred to as a net listing), and of then performing a weighting calculation process during which a movement range for a cell becomes smaller as the weighting for the cell becomes greater, while weighting is significantly enhanced for a cell for which the timing margin is small; and

a cell placement step of placing a cell in accordance with weighting results obtained at the first weight determination step.

2. The design method for a semiconductor integrated circuit according to claim 1, further comprising:

a second weighting determination step of performing a weighting calculation process during which a movement range for a cell becomes smaller as the weighting for the cell becomes greater, while the weighting is significantly enhanced for a cell for which, based on physical information, a long Manhattan distance is obtained; and

a cell placement step of placing cells in accordance with the weighting results obtained at the second weighting determination step.

3. The design method for a semiconductor integrated circuit according to claim 1, further comprising:

a third weighting determination step of performing a weighting calculation process during which a movement range for a cell becomes smaller as the weighting for the cell becomes greater, while the weighting is significantly enhanced for a cell for which a large number of fanouts is obtained from a net listing at a physical design step for a semiconductor integrated circuit; and

a cell placement step of placing cells in accordance with weighting results obtained at the third weight determination step.

4. The design method for a semiconductor integrated circuit according to claim 1, further comprising:

a setup step of employing the weighting results obtained at least one of the first to the third weight determination steps to designate a permissible value for a movement range for a cell.

5. The design method for a semiconductor integrated circuit according to claim 4, further comprising:

a storage step of storing the movement range designated at the setup step; and

a determination step of searching for an area, within the permissible value designated for the movement range, whereat the tiling ratio of cells becomes smallest, and determining a movement range for a cell, while avoiding a cell or wiring congested area.

6. The design method for a semiconductor integrated circuit according to claim 5, further comprising:

a change step of employing a signal pin density to change the movement range that is determined at the determination step.

7. The design method for a semiconductor integrated circuit according to claim 6, wherein the storage step includes the steps of:

extending the movement range in accordance with a predetermined ratio when an area that satisfies a cell placement condition is not obtained at the change step for changing the movement range based on the signal pin density, and determining an upper limit for the movement range in accordance with the driving capability of a cell; and

determining, within a range extending to the upper limit, a position to which to move the cell.

8. The design method for a semiconductor integrated circuit according to claim 6, further comprising a step of:

when an area that satisfies a placement condition is obtained at the change step, identifying a drive capability for a cell based on an area obtained at the storage area, and changing the drive capability to acquire an area for placing the cell.

9. The design method for a semiconductor integrated circuit according to claim 1, further comprising a step of:

when wiring passes through a congested area, reducing the effectiveness of a cell on a reception side, and placing, adjacent to the cell, another cell having an appropriate driving capability.

10. The design method for a semiconductor integrated circuit according to claim 9, further comprising a step of inserting a repeater cell when a timing margin is high.

11. The design method for a semiconductor integrated circuit according to claim 9, wherein dimensional reduction or logic reduction is performed by preferentially replacing a cell, in a congested location, that has a high timing margin with a low-power driven cell, so that congestion engendered by placing cells is relieved and acquisition of a cell area is ensured.

12. A design apparatus for a semiconductor integrated circuit comprising:

a first weight determination unit for first receiving timing information and connection information, and for then performing a weighting calculation process during which a movement range for a cell becomes smaller as the weighting for the cell becomes greater, while weighting is significantly enhanced for a cell for which the timing margin is small; and

a cell placement unit for placing a cell in accordance with weighting results obtained by the first weight determination unit.

13. The design apparatus for a semiconductor integrated circuit according to claim 12, further comprising:

a second weighting determination unit for performing a weighting calculation process during which a movement range for a cell becomes smaller as the weighting for the cell becomes greater, while the weighting is significantly enhanced for a cell for which, based on physical information, a long Manhattan distance is obtained,

wherein the cell placement unit places cells in accordance with the weighting results obtained by the first weighting determination unit and second weighting determination unit.

14. The design apparatus for a semiconductor integrated circuit according to claim 12, further comprising:

a third weighting determination unit for performing a weighting calculation process during which a movement range for a cell becomes smaller as the weighting for the cell becomes greater, while the weighting is significantly enhanced for a cell for which a large number of fanouts is obtained from a net listing,

wherein the cell placement unit places cells in accordance with the weighting results obtained by the third weight determination unit and the weighting results obtained by either the first or the second weighting determination unit.

15. The design apparatus for a semiconductor integrated circuit according to claim 12, further comprising:

a movement range setup unit for employing the weighting results obtained by at least one of the first to the third weight determination units to designate a permissible value for a movement range for a cell.

16. The design apparatus for a semiconductor integrated circuit according to claim 15, further comprising:

a movement range storage unit for storing the movement range designated by the movement range setup unit; and

a movement range determination unit for searching for an area, within the permissible value designated for the movement range, whereat the tiling ratio of cells becomes smallest, and for determining a movement range for a cell, while avoiding a cell or wiring congested area.

17. The design apparatus for a semiconductor integrated circuit according to claim 16, further comprising:

a movement range change unit for employing a signal pin density to change the movement range that is determined by the movement range determination unit.

18. The design apparatus for a semiconductor integrated circuit according to claim 17, wherein the movement range storage unit includes:

a movement range extension unit for extending the movement range in accordance with a predetermined ratio when an area that satisfies a cell placement condition is not found based on the results obtained by the movement range change unit, and for determining an upper limit for the movement range in accordance with the driving capability of a cell; and

a movement position determination unit for determining, within a range extending to the upper limit, a position to which to move the cell.

19. The design apparatus for a semiconductor integrated circuit according to claim 17, further comprising:

a cell placement unit for, when an area that satisfies a placement condition is obtained by the movement range change unit, identifying a drive capability for a cell based on an area obtained by the movement range storage area, and for changing the drive capability to acquire an area for placing the cell.

20. The design apparatus for a semiconductor integrated circuit according to claim 12, wherein, when wiring passes through a congested area, the cell placement unit reduces the effectiveness of a cell on a reception side, and places, adjacent to the cell, another cell having an appropriate driving capability.

21. The design apparatus for a semiconductor integrated circuit according to claim 20, wherein the cell placement unit inserts a repeater cell when a timing margin is high.

22. The design apparatus for a semiconductor integrated circuit according to claim 20, wherein dimensional reduction or logic reduction is performed by preferentially replacing a cell, in a congested location, that has a high timing margin with a low-power driven cell, so that congestion engendered by placing cells is relieved and acquisition of a cell area is ensured.