OPTIMISED COMPILATION METHOD DURING CONDITIONAL BRANCHING

• US 20090019431A1
• Filed: 02/24/2007
• Published: 01/15/2009
• Est. Priority Date: 03/02/2006
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Thomas, Bijo, George, Tomson
• Application Number:
  US12/281,371
• Publication Number:
  US 20090019431A1
• Time in Patent Office: Days
• US Class Current: 717/151
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836

Abstract

The present invention discloses a compilation method of a program code in a digital device in a profile driven compilation. An approach for optimizing the execution of program code by providing additional intelligence to the compiler is provided, where the compiler decides whether to have single decision tree with guarded operations or multiple decision trees. The method of this invention is helpful, in reducing the overhead of conditional code branching to have an optimised program code, both in compiler driven optimisations and in manual optimisations by the programmer.

Claims

1. A compilation method of a program code in a digital device, wherein said program code comprises a main code and a branch code, in a profile driven compilation, comprising the steps of:

determining a branch code load of the branch code, wherein said branch code load comprises a number of very long instruction words, wherein the very long instruction words comprises jump instructions in the branch codes;

determining a frequency of execution of the branch code during the execution of the preliminary compilation, wherein said preliminary compilation is first stage of said profile driven compilation;

determining an increased main code load, wherein said increased main code load comprises an additional load created by using a single decision tree with guarding operation;

determining a frequency of execution of said main code during execution of the preliminary compilation; and

deciding whether the processing load of executing the branch code is less than a threshold limit and, if so, creating a separate decision tree for the branch code,

deciding whether the processing load of executing the branch code is greater than a threshold limit and, if so, using guarding operations to incorporate the branch code as part of the decision tree of the main code.

2. The method of claim 1, wherein said processing load of executing the branch code is determined by a product of the branch code load and said frequency of execution of the branch code of the preliminary compilation

3. The method of claim 1, whereby a compiler deciding between guarded operations or a separate decision tree for the execution of the branch code.

4. The method of claim 1, wherein said threshold limit is determined by a product of the increased main code load and the frequency of execution of the main code during preliminary compilation.

5. The method of claim 1, wherein the branch code comprises conditional instructions in the program code.

6. The method of claim 1, wherein said digital device comprises a computer and the program code comprises a computer program code.

7. The method of claim 1, wherein the frequency of execution of the branch code and the frequency of execution of the main code is fed into a compiler after an execution of the preliminary compilation.

8. The method of claim 1, wherein said method is applied to a compiler chain of a plurality of very long instruction word processors.