GRAPHENE-BASED TRANSISTOR

• US 20090020764A1
• Filed: 07/16/2007
• Published: 01/22/2009
• Est. Priority Date: 07/16/2007
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward J., Anderson, Brent A.
• Granted Patent: US 7,732,859 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
• CPC Class Codes: H01L 29/7781 with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

A graphene layer is formed on a surface of a silicon carbide substrate. A dummy gate structure is formed over the fin, in the trench, or on a portion of the planar graphene layer to implant dopants into source and drain regions. The dummy gate structure is thereafter removed to provide an opening over the channel of the transistor. Threshold voltage adjustment implantation may be performed to form a threshold voltage implant region directly beneath the channel, which comprises the graphene layer. A gate dielectric is deposited over a channel portion of the graphene layer. After an optional spacer formation, a gate conductor is formed by deposition and planarization. The resulting graphene-based field effect transistor has a high carrier mobility due to the graphene layer in the channel, low contact resistance to the source and drain region, and optimized threshold voltage and leakage due to the threshold voltage implant region.

Claims

1. A field effect transistor comprising:

a silicon carbide fin located directly on a silicon carbide substrate;

a pair of graphene layers located on a pair of sidewalls of said silicon carbide fin;

doped source and drain regions located between said pair of graphene layers and within said silicon carbide fin;

a gate dielectric directly contacting said pair of graphene layers; and

a gate electrode directly contacting said gate dielectric.

2. The field effect transistor of claim 1, further comprising a threshold voltage adjustment implant region located within said silicon carbide fin and abutting said pair of graphene layers.

3. The field effect transistor of claim 1, further comprising:

a first planar graphene layer located on a top surface of said silicon carbide substrate;

a second planar graphene layer located on a top surface of said silicon carbide fin;

a first insulator layer directly contacting said first planar graphene layer; and

a second insulator layer directly contacting said second planar graphene layer, wherein said first insulator layer and said second insulator layer comprise the same material.

4. The field effect transistor of claim 1, further comprising a gate level dielectric having a top surface which is substantially coplanar with said gate electrode.

5. The field effect transistor of claim 4, wherein said gate level dielectric has at least one sidewall which abuts said gate dielectric.

6. A field effect transistor comprising:

a trench having a substantially flat bottom surface and a pair of trench sidewalls and located within a silicon carbide substrate;

a graphene layer located directly on said substantially flat bottom surface of said trench;

doped source and drain regions located on said pair of trench sidewalls and within said silicon carbide substrate;

a gate dielectric directly contacting said graphene layer; and

a gate electrode directly contacting said gate dielectric.

7. The field effect transistor of claim 6, further comprising a threshold voltage adjustment implant region located directly beneath said graphene layer and within said silicon carbide substrate.

8. The field effect transistor of claim 7, further comprising at least one halo region abutting said threshold voltage adjustment implant region and one of said doped source and drain regions.

9. The field effect transistor of claim 6, further comprising a dielectric spacer, wherein said gate dielectric contains at least a pair of substantially vertical sidewalls which abut said dielectric spacer.

10. A field effect transistor comprising:

a planar graphene layer located directly on a surface of a silicon carbide substrate;

doped source and drain regions located beneath said graphene layer and within said silicon carbide substrate;

a gate dielectric directly contacting said planar graphene layer; and

a gate electrode directly contacting said gate dielectric.

11. The field effect transistor of claim 10, further comprising a threshold voltage adjustment implant region located directly beneath said planar graphene layer and within said silicon carbide substrate.

12. The field effect transistor of claim 10, further comprising a gate level dielectric having a top surface which is substantially coplanar with said gate electrode.

13. The field effect transistor of claim 10, further comprising a dielectric spacer, wherein said gate dielectric contains at least a pair of substantially vertical sidewalls which abut said dielectric spacer.

14. A method of manufacturing a field effect transistor comprising:

providing a silicon carbide substrate;

forming at least one graphene layer on said silicon carbide substrate;

forming an ion implantation blocking structure over a portion of said at least one graphene layer;

forming doped source and drain regions within said silicon carbide substrate;

removing said ion implantation blocking structure;

forming a gate dielectric over said portion of said at least one graphene layer; and

forming a gate electrode directly on said gate dielectric layer.

15. The method of claim 14, further comprising forming a threshold voltage adjustment implant region beneath said at least one graphene layer.

16. The method of claim 14, further comprising forming a silicon carbide fin directly on said silicon carbide substrate, wherein said at least one graphene layer is a pair of graphene layers on a pair of sidewalls of said silicon carbide fin.

17. The method of claim 14, further comprising forming a trench in said silicon carbide substrate, wherein said at least one graphene layer is a graphene layer on a substantially flat bottom surface of said trench.

18. The method of claim 14, further comprising forming a gate spacer, wherein said gate dielectric contains at least one substantially vertical portion that abuts said gate spacer.

19. The method of claim 14, further comprising forming a gate level dielectric over said silicon carbide substrate in an area outside said ion implantation blocking structure.

20. The method of claim 14, wherein said gate electrode is formed by depositing a gate electrode material and planarizing said gate electrode material employing a stopping layer which is selected from the group consisting of said gate dielectric, a surface of said silicon carbide substrate, and a gate level dielectric.