Method of Forming Power Device Utilizing Chemical Mechanical Planarization

• US 20090020810A1
• Filed: 09/30/2008
• Published: 01/22/2009
• Est. Priority Date: 01/05/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Bruce Douglas Marchant
• Inventors: Marchant, Bruce Douglas
• Granted Patent: US 7,772,642 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 438/942 Masking
• CPC Class Codes: Y10S 438/95 Multilayer mask including nonradiation sensitive layer

Abstract

A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench.

Claims

1-51. -51. (canceled)

52. A field effect transistor comprising:

a plurality of active gate trenches in a silicon region, each active gate trench including a recessed gate electrode;

a gate runner trench in the silicon region, the gate runner trench being contiguous with the plurality of active gate trenches, the gate runner trench including a recessed gate runner, the recessed gate runner being contiguous with and thus in electrical contact with the recessed gate electrodes, wherein the gate runner trench has a width greater than a width of each of the plurality of active gate trenches.

53. The field effect transistor of claim 52 wherein the width of the gate runner trench is at least three times greater than the width of each active gate trench.

54. The field effect transistor of claim 52 wherein the plurality of active gate trenches and the gate runner trench extend to substantially the same depth within the silicon region.

55. The field effect transistor of claim 52 wherein the gate runner trench includes a dielectric layer extending beneath the recessed gate runner which has a greater thickness than a thickness of a dielectric layer extending beneath each recessed gate electrode in the plurality of active gate trenches.

56. The field effect transistor of claim 52 wherein the plurality of active gate trenches extend perpendicularly to the at least one gate runner trench.

57. The field effect transistor of claim 52 wherein the silicon region has a first conductivity type, the field effect transistor further comprising:

a well region of a second conductivity type in the silicon region;

source regions of the first conductivity type in the well region, the source regions flanking the plurality of active gate trenches; and

a first metal layer electrically contacting the well region and the source regions, and a second metal layer contacting the recessed gate runner.

58-106. -106. (canceled)