DRIVING DEVICE, DISPLAY APPARATUS HAVING THE SAME AND METHOD OF DRIVING THE DISPLAY APPARATUS

• US 20090021507A1
• Filed: 06/25/2008
• Published: 01/22/2009
• Est. Priority Date: 07/20/2007
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Sang-Hoon, KIM, Hun-Tae, LEE, Cheol-Ho, BAE, Hyeon-Seok
• Granted Patent: US 8,379,011 B2
• Time in Patent Office: Days
• US Class Current: 345/212
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0276 for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
• CPC Class Codes: G09G 2330/04 Display protection
• CPC Class Codes: G09G 3/3666 with the matrix divided into sections
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers
• CPC Class Codes: G09G 5/003 Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto specific for a CRT G09G1/165; for a flat panel G09G3/2092

Abstract

A driving device includes an output timing controller which controls an output timing of a first driving voltage and a second driving voltage respectively generated from a first voltage generator and a second voltage generator. A third driving voltage output from the output timing controller is provided to a first data driver and a second data driver, and also provided to a gamma voltage generator to generate a plurality of gamma voltages. Accordingly, a reverse electric potential between the third driving voltage and the gamma voltages is prevented from being generated in the first and second data drivers, therefore, preventing the first and second data drivers from being damaged.

Claims

1. A driving device comprising:

a first voltage generator which receives a power voltage from an exterior power source and outputs a first driving voltage;

a second voltage generator which receives the power voltage and outputs a second driving voltage;

an output timing controller which receives the first and second driving voltages from the first and second voltage generators, respectively, and outputs a third driving voltage at a predetermined time;

a gamma voltage generator which receives the third driving voltage from the output timing controller and outputs a plurality of gamma voltages;

a first data driver which operates in response to the third driving voltage from the output timing controller to change a first image signal to a first data signal based on the gamma voltages provided from the gamma voltage generator; and

a second data driver which operates in response to the third driving voltage from the output timing controller to change a second image data to a second data signal based on the gamma voltages provided from the gamma voltage generator.

2. The driving device of claim 1, wherein the output timing controller comprises an AND-gate configuration which outputs the third driving voltage when both the first and second driving voltages are in a high state.

3. The driving device of claim 2, wherein the output timing controller comprises:

a first transistor comprising an input electrode which receives the first driving voltage, a control electrode which receives the second driving voltage, and an output electrode connected to a first output terminal of the output timing controller, the first transistor which outputs the third driving voltage to the first output terminal in response to the second driving voltage; and

a second transistor comprising an input electrode which receives the second driving voltage, a control electrode which receives the first driving voltage, and an output electrode connected to a second terminal of the output timing controller, the second transistor outputs the third driving voltage to the second output terminal in response to the first driving voltage.

4. The driving device of claim 3, wherein the first data driver is connected to the first output terminal of the output timing controller and receives the third driving voltage, the second data driver is connected to the second output terminal of the output timing controller and receives the third driving voltage, and the gamma voltage generator is connected to either the first output terminal or the second output terminal of the output timing controller and receives the third driving voltage.

5. A driving device comprising:

a plurality of voltage generators which receive a power voltage from an exterior power source and output a plurality of driving voltages, respectively;

an output timing controller which receive the driving voltages from the voltage generators and output a common driving voltage at a predetermined time in response to a timing control signal;

a gamma voltage generator which receives the common driving voltage from the output timing controller to output a plurality of gamma voltages; and

a plurality of data drivers which operate in response to the common driving voltage from the output timing controller and change an image signal to a data signal based on the gamma voltages provided from the gamma voltage generator.

6. The driving device of claim 5, wherein the output timing controller comprises a plurality of transistors connected between a plurality of input terminals respectively receive the driving voltages and a plurality of output terminals output the common driving voltage,

each transistor comprises an input electrode connected to a corresponding input terminal among the input terminals, a control electrode which receives the timing control signal, and an output electrode connected to a corresponding output terminal among the output terminals, and

each transistor outputs the common driving voltage to the corresponding output terminal in response to the timing control signal.

7. The driving device of claim 6, wherein the timing control signal is in a high state during a period where the driving voltages are generated in the high state, and each of the transistors outputs the common driving voltage having the high state in response to the timing control signal having the high state.

8. The driving device of claim 5, further comprising a timing controller which generates the timing control signal and provides the timing control signal to the output timing controller.

9. A display apparatus comprising:

a first voltage generator which receives a power voltage from an exterior to output a first driving voltage;

a second voltage generator which receives the power voltage to output a second driving voltage;

an output timing controller which receives the first and second driving voltages from the first and second voltage generators, respectively, and outputs a third driving voltage at a predetermined time;

a gamma voltage generator which receives the third driving voltage from the output timing controller to output a plurality of gamma voltages;

a first data driver which operates in response to the third driving voltage from the output timing controller to change a first image signal to a first data signal based on the gamma voltages provided from the gamma voltage generator;

a second data driver which operates in response to the third driving voltage from the output timing controller to change a second image signal to a second data signal based on the gamma voltages provided from the gamma voltage generator;

a gate driver which receives a gate-on voltage and a gate-off voltage output from either the first voltage generator or the second voltage generator and sequentially outputs a gate signal; and

a display panel which receives the first and second data signals in response to the gate signal to display an image.

10. The display apparatus of claim 9, wherein the output timing controller comprises an AND-gate configuration which outputs the third driving voltage when both the first and second driving voltages are in a high state.

11. The display apparatus of claim 10, wherein the timing controller comprises:

a first transistor comprising an input electrode which receives the first driving voltage, a control electrode which receives the second driving voltage, and an output electrode connected to a first output terminal of the output timing controller, the first transistor outputs the third driving voltage to the first output terminal in response to the second driving voltage; and

a second transistor comprising an input electrode which receives the second driving voltage, a control electrode which receives the first driving voltage, and an output electrode connected to a second output terminal of the output timing controller, the second transistor outputs the third driving voltage to the second output terminal in response to the first driving voltage.

12. The display apparatus of claim 10, wherein the first data driver is connected to the first output terminal of the output timing controller and receives the third driving voltage, the second data driver is connected to the second output terminal of the output timing controller and receives the third driving voltage, and the gamma voltage generator is connected to one of the first and second output terminals of the output timing controller and receives the third driving voltage.

13. The display apparatus of claim 9, further comprising a timing controller which generates a timing control signal and provides the timing control signal to the output timing controller.

14. The display apparatus of claim 13, wherein the output timing controller comprises:

a third transistor comprising an input electrode which receives the first driving voltage, a control electrode which receives the timing control signal, and an output electrode connected to a first output terminal of the output timing controller, the third transistor outputs the third driving voltage to the first output terminal in response to the timing control signal; and

a fourth transistor comprising an input electrode which receives the second driving voltage, a control electrode receiving the timing control signal, and an output electrode connected to a second output terminal of the output timing controller, the fourth transistor outputs the third driving voltage to the second output terminal in response to the timing control signal.

15. The display apparatus of claim 14, wherein the timing control signal is in a high state during a period where both the first and second driving voltages are generated in the high state, and the first and second transistors output the third driving voltage having the high state in response to the timing control signal having the high state.

16. The display apparatus of claim 9, further comprising a main printed circuit board on which the first and second voltage generators, the output timing controller, and the gamma voltage generator are mounted.

17. The display apparatus of claim 16, further comprising:

first and second printed circuit boards which each receive the third driving voltage and the gamma voltages from the main printed circuit board and are electrically connected to the first and second data drivers, respectively;

a first tape carrier package interposed between the first printed circuit board and the display panel; and

a second tape carrier package interposed between the second printed circuit board and the display panel.

18. The display apparatus of claim 17, wherein the first and second data drivers comprises a plurality of first data driving chips and a plurality of second data driving chips, respectively, and the first and second data driving chips are mounted on the first and second tape carrier packages, respectively.

19. The display apparatus of claim 18, wherein the display panel comprises:

a plurality of gate lines which sequentially receives the gate signal from the gate driver;

a plurality of first data lines which insulate from and intersect with the gate lines, the first data lines receive the first data signal from the first data driving chips; and

a plurality of second data lines which insulate from and intersect with the gate lines, the second data lines which receive the second data signal from the second data driving chips.

20. The display apparatus of claim 19, wherein the first data lines are arranged at a left side with respect to an imaginary line crossing a center of the display panel to be parallel to the first data lines, and the second data lines are arranged at a right side with respect to the imaginary line.

21. The display apparatus of claim 9, wherein the first and second driving voltages include a different voltage level from each other as a time lapses.

22. The display apparatus of claim 21, wherein the second driving voltage is generated later than the first driving voltage.

23. A method of driving a display apparatus, comprising:

receiving a power voltage and outputting a first driving voltage and a second driving voltage;

outputting a third driving voltage when the first and second driving voltages are in a high state;

outputting a plurality of gamma voltages in response to the third driving voltage;

changing a first image signal to a first data signal in response to the third driving voltage based on the gamma voltages;

changing a second image signal to a second data signal in response to the third driving voltage based on the gamma voltages;

sequentially outputting a gate signal; and

displaying an image corresponding to the first and second data signals in response to the gate signal,

wherein the first driving voltage and the second driving voltage change from the low state to the high state at a different time.

24. The method of claim 23, further comprising outputting the third driving voltage in response to a timing control signal generated when both the first and second driving voltages are in the high state.