HIGH DYNAMIC RANGE CASCADED INTEGRATION PIXEL CELL AND METHOD OF OPERATION

• US 20090021627A1
• Filed: 09/24/2008
• Published: 01/22/2009
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Fossum, Eric R.
• Granted Patent: US 7,990,449 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

A cascaded imaging storage system for a pixel is disclosed for improving intrascene dynamic range. Charges accumulated in a first capacitor spill over into a second capacitor when a charge storage capacity of the first capacitor is exceeded. A third capacitor may also be provided such that charges accumulated by said second capacitor spill over into the third capacitor when the charge storage capacity of the second capacitor is exceeded.

Claims

1-79. -79. (canceled)

80. A semiconductor device comprising:

a photo-conversion node;

a first charge storage node configured to store charge generated by the photo-conversion node; and

a second charge storage node configured to store charge generated by the photo-conversion node when the charge exceeds a limit.

81. The semiconductor device of claim 80, wherein the limit is the charge storage capacity of the first charge storage node.

82. The semiconductor device of claim 81, wherein the second charge storage node has a greater charge storage capacity than the first charge storage node.

83. The semiconductor device of claim 81, further comprising a third charge storage node configured to store charge generated by the photo-conversion node when the charge exceeds the combined storage capacity of the first and second charge storage nodes.

84. The semiconductor device of claim 83, wherein the third charge storage node has a greater charge storage capacity than the second charge storage node, and the second charge storage node has a greater charge storage capacity than the first charge storage node.

85. The semiconductor device of claim 80, wherein the photo-conversion node is a photodiode.

86. The semiconductor device of claim 80, wherein the first charge storage node is a conductor coupled to the photo-conversion device and exhibits parasitic capacitance.

87. The semiconductor device of claim 80, wherein the first charge storage node is a discrete capacitor.

88. The semiconductor device of claim 86, wherein the second charge storage node is a discrete capacitor.

89. The semiconductor device of claim 80, further comprising a transistor coupled between the first and second charge storage nodes and configured to transfer charge to the second charge storage node when the charge exceeds the limit.

90. The semiconductor device of claim 83, further comprising a second transistor coupled between the second and third charge storage nodes and configured to transfer charge to the third charge storage node when the charge exceeds the combined storage capacity of the first and second charge storage nodes.

91. An imager, comprising:

a photo-sensitive device; and

a plurality of charge storage nodes coupled to the photo-sensitive device,

wherein a first of the plurality of charge storage nodes is configured to store charge generated by the photo-sensitive device up to a threshold level and a second of the plurality of charge storage nodes is configured to store charge above the threshold level.

92. The imager of claim 91, wherein each of the plurality of charge storage nodes has a different storage capacity.

93. The imager of claim 91, wherein the first charge storage node has less storage capacity than the second charge storage node.

94. The imager of claim 91, wherein a third of the plurality of charge storage nodes is configured to store charge above a second threshold level.

95. The imager of claim 94, wherein the first charge storage node has less storage capacity than the second charge storage node, and the second charge storage node has less storage capacity than the third charge storage node.

96. The imager of claim 92, wherein each of the plurality of charge storages nodes is configured to store charge generated by the photo-sensitive device when the charge exceeds the combined storage capacity of the charge storage nodes of lesser storage capacity.

97. The imager of claim 91, wherein at least one of the plurality of charge storage nodes is a region of parasitic capacitance.

98. The imager of claim 91, wherein at least one of the plurality of charge storage nodes is a discrete capacitor.

99. The imager of claim 91, wherein the first charge storage node is a region of parasitic capacitance and the second charge storage node is a discrete capacitor.

100. The imager of claim 91, wherein the imager is a CMOS imager.

101. A method for operating an imager, comprising:

converting light into an electric charge; and

storing the electric charge in a sequence of charge storage regions,

wherein a subsequent charge storage region in the sequence of charge storage regions is configured to store a portion of the electric charge when the electric charge exceeds the combined storage capacity of the prior charge storage regions in the sequence of charge storage regions.

102. The method of operating an imager of claim 101, wherein each subsequent charge storage region in the sequence of charge storage regions has a storage capacity greater than each of the prior charge storage regions in the sequence of charge storage regions.

103. The method of operating an imager of claim 101, wherein the sequence of charge storage regions comprises three charge storage regions.

104. The method of operating an imager of claim 101, further comprising turning on a transistor coupled between the first and second charge storage regions in the sequence of charge storage regions when the electric charge exceeds the storage capacity of the first charge storage region.

105. The method of operating an imager of claim 101, wherein at least one of the sequence of charge storage regions is a discrete capacitor.