Wire bonded wafer level cavity package

• US 20090023249A1
• Filed: 09/15/2008
• Published: 01/22/2009
• Est. Priority Date: 03/22/2005
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Humpston, Giles, Tuckerman, David B., Honer, Kenneth Allen, Nystrom, Michael J.
• Granted Patent: US 7,858,445 B2
• Time in Patent Office: Days
• US Class Current: 438/113
• CPC Class Codes: B81B 7/0006 Interconnects
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

A microelectronic device includes a chip having a front surface and a rear surface, the front surface having an active region and a plurality of contacts exposed at the front surface outside of the active region. The device further includes a lid overlying the front surface. The lid has edges bounding the lid, at least one of the edges including one or more outer portions and one or more recesses extending laterally inwardly from the outer portions, with the contacts being aligned with the recesses and exposed through them.

Claims

1. A method of making a microelectronic device comprising:

(a) assembling a lid element with a wafer element, the wafer element having a front surface including a plurality of regions, each such region including an active area and a plurality of contacts exposed at said front surface outside of said active area, said lid element overlying said front surface of said wafer element;

then

(b) forming holes in said lid element so as to expose said contacts; and

(c) severing said wafer element and said lid element along severance lines intersecting said holes to thereby form a plurality of units, each such unit including a lid having one or more edges with recesses formed from said holes.

2. A method as claimed in claim 1, wherein said hole-forming step is performed so that said holes are elongated in directions transverse to said severance lines.

3. A method as claimed in claim 1, wherein said lid element has an outer surface and an inner surface, said assembling step is performed so that said outer surface faces upwardly, away from said wafer unit, and said hole-forming step is performed so that said holes taper inwardly a downward direction from said outer surface toward said inner surface.

4. A method as claimed in claim 1, wherein said hole-forming step is performed so that a plurality of contacts are exposed within each hole.

5. A method as claimed in claim 4, wherein the plural contacts exposed within each hole include at least one contact in each of two adjacent regions of the wafer unit.

6. A method as claimed in claim 5, wherein the plural contacts exposed within each hole include two or more contacts in each of two adjacent regions of the wafer unit.

7. A method as claimed in claim 1, further comprising providing a seal extending between said wafer unit and said lid element, said seal overlying said contacts, and forming holes in said seal in alignment with said holes in said lid element prior to said severing step.

8. A method as claimed in claim 1, further comprising testing said wafer unit by applying one or more test probes to said contacts through said holes prior to said severing step.

9. A method as claimed in claim 1, wherein, prior to said hole-forming step, said lid element has planar inner and outer surfaces.

42. The device of claim 1 wherein each recess has two sloping surfaces defining an angle between about five degrees and about sixty degrees.

43. The device of claim 1 wherein said one or more recesses have dimensions decreasing progressively from said outer surface of said lid to said front surface of said chip.

10. A method of making microelectronic devices comprising:

(a) assembling a lid element having substantially planar inner and outer surfaces with a wafer element having a front surface including a plurality of regions, each such region including an active area and a plurality of contacts exposed at said front surface in a peripheral area outside of said active area, so that the lid element overlies the front surface of the wafer element with the inner surface spaced from the front surface of the wafer element;

then

(b) removing portions of the lid element overlying said peripheral areas so as to expose contacts of the wafer element; and

then

(c) severing the wafer element along severance lines extending between peripheral areas of adjacent regions.

11. A method as claimed in claim 10, further comprising providing a seal extending between said chip and said lid, portions of said seal extending over said peripheral areas of the wafer element and said contacts, and removing said extending portions of said seal after said step of removing portions of said lid element.

12. A method of making microelectronic devices comprising:

(a) assembling a lid element having an outer surface and an inner surface having grooves therein with a wafer element having a front surface including a plurality of regions, each such region including an active area and a plurality of contacts exposed at said front surface in a peripheral area outside of said active area, so that the lid element overlies the front surface of the wafer element with the inner surface facing toward the wafer element and with the grooves aligned with the peripheral areas of the wafer element;

then

(b) thinning the lid element from the outer surface until the grooves form channels extending entirely through the lid element in alignment with the peripheral areas of the wafer unit, thereby subdividing the lid element into individual lids overlying the active areas of the wafer unit; and

then

(c) severing the wafer element along severance lines extending between peripheral areas of adjacent regions.

13. A method of making microelectronic devices comprising:

(a) assembling a lid element with a wafer element, said wafer element having a plurality of regions, each region including a plurality of contacts;

(b) forming holes in the lid element so as to expose said contacts;

(c) depositing an electrically conductive material into said holes; and

(d) severing said wafer element and said lid element along severance lines intersecting said electrically conductive material to thereby form of plurality of units, each unit having an outer edge with recesses in said lid and said electrically conductive material in said recesses.

14. The method of making a microelectronic device according to claim 13, wherein the step of depositing said electrically conductive material includes transferring a molten electrically conductive material into said holes and cooling said molten electrically conductive material.

15. A method of making a microelectronic assembly comprising:

(a) placing a unit having a chip, a lid overlying a front surface of the chip, and recesses in said lid open at an edge of the lid with electrically conductive material in said recesses in proximity to a substrate having conductive pads with said lid facing upwardly away from the substrate; and

(b) heating said electrically conductive material such that said electrically conductive material flows out of said recesses, across said edge and onto said conductive pads on said substrate.

16. A method as claimed in claim 15 wherein said placing step includes placing the unit into a recess in the substrate so that contacts on the chip disposed in the recesses are vertically aligned with the conductive pads on the substrate.

17-41. -41. (canceled)