MEMORY CIRCUIT SYSTEM AND METHOD
First Claim
Patent Images
1. A sub-system, comprising:
- an interface circuit adapted for coupling with a plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits;
wherein the at least one aspect includes at least one of a signal, a capacity, a timing, and a logical interface.
3 Assignments
0 Petitions
Accused Products
Abstract
A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).
-
Citations
20 Claims
-
1. A sub-system, comprising:
-
an interface circuit adapted for coupling with a plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits; wherein the at least one aspect includes at least one of a signal, a capacity, a timing, and a logical interface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
-
-
19. A method, comprising:
-
interfacing a plurality of memory circuits and a system; and emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits; wherein the at least one aspect includes at least one of a signal, a capacity, a timing, and a logical interface.
-
-
20. A system, comprising:
-
a plurality of memory circuits; and an interface circuit in communication with the plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits; wherein the at least one aspect includes at least one of a signal, a capacity, a timing, and a logical interface.
-
Specification