MEMORY CIRCUIT SYSTEM AND METHOD

• US 20090024789A1
• Filed: 10/30/2007
• Published: 01/22/2009
• Est. Priority Date: 07/18/2007
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Wang, David T., Smith, Michael John Sebastian, Weber, Frederick Daniel, Schakel, Keith R., Rajan, Suresh Natarajan
• Granted Patent: US 8,209,479 B2
• Time in Patent Office: Days
• US Class Current: 711/105
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).

Claims

1. A sub-system, comprising:

an interface circuit adapted for coupling with a plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits;

wherein the at least one aspect includes at least one of a signal, a capacity, a timing, and a logical interface.

2. The sub-system of claim 1, wherein the at least one aspect includes the signal.

3. The sub-system of claim 2, wherein the signal is selected from the group consisting of an address signal, a control signal, and a data signal.

4. The sub-system of claim 1, wherein the at least one aspect includes the capacity.

5. The sub-system of claim 4, wherein the capacity includes a memory capacity.

6. The sub-system of claim 5, wherein the memory capacity relates to a number of the memory circuits.

7. The sub-system of claim 5, wherein the interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with a first memory capacity that is greater than a second memory capacity of at least one of the plurality of memory circuits.

8. The sub-system of claim 1, wherein the at least one aspect includes the timing.

9. The sub-system of claim 8, wherein the timing relates to a latency.

10. The sub-system of claim 9, wherein the latency includes a column address strobe (CAS) latency.

11. The sub-system of claim 10, wherein the interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with a first CAS latency that is longer than a second CAS latency of at least one of the plurality of memory circuits.

12. The sub-system of claim 9, wherein the latency includes a row address strobe (RAS) to CAS latency (tRCD).

13. The sub-system of claim 12, wherein the interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with a first tRCD that is longer than a second tRCD of at least one of the plurality of memory circuits.

14. The sub-system of claim 9, wherein the latency includes a row precharge latency (tRP).

15. The sub-system of claim 14, wherein the interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with a first tRP that is longer than a second tRP of at least one of the plurality of memory circuits.

16. The sub-system of claim 9, wherein the latency includes an activate to precharge latency (tRAS).

17. The sub-system of claim 1, wherein the at least one aspect includes the logical interface.

18. The sub-system of claim 1, wherein the memory circuits each include dynamic random access memory (DRAM).

19. A method, comprising:

interfacing a plurality of memory circuits and a system; and

emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits;

wherein the at least one aspect includes at least one of a signal, a capacity, a timing, and a logical interface.

20. A system, comprising:

a plurality of memory circuits; and

an interface circuit in communication with the plurality of memory circuits and a system, the interface circuit operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits;

wherein the at least one aspect includes at least one of a signal, a capacity, a timing, and a logical interface.