MULTIPLE-CORE PROCESSOR WITH HIERARCHICAL MICROCODE STORE

• US 20090024836A1
• Filed: 07/18/2007
• Published: 01/22/2009
• Est. Priority Date: 07/18/2007
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lie, Sean, Shen, Gene W., Holloway, Bruce R., Butler, Michael G.
• Granted Patent: US 7,743,232 B2
• Time in Patent Office: Days
• US Class Current: 712/211
• CPC Class Codes: G06F 9/223 Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
• CPC Class Codes: G06F 9/28 Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel

Abstract

A multiple-core processor having a hierarchical microcode store. A processor may include multiple processor cores, each configured to independently execute instructions defined according to a programmer-visible instruction set architecture (ISA). Each core may include a respective local microcode unit configured to store microcode entries. The processor may also include a remote microcode unit accessible by each of the processor cores. Any given one of the processor cores may be configured to generate a given microcode entrypoint corresponding to a particular microcode entry including one or more operations to be executed by the given processor core, and to determine whether the particular microcode entry is stored within the respective local microcode unit of the given core. In response to determining that the particular microcode entry is not stored within the respective local microcode unit, the given core may convey a request for the particular microcode entry to the remote microcode unit.

Claims

1. A processor, comprising:

a plurality of processor cores, each configured to independently execute instructions defined according to a programmer-visible instruction set architecture (ISA), wherein each of said plurality of processor cores includes a respective local microcode unit configured to store microcode entries; and

a remote microcode unit accessible by each of said processor cores and including a remote microcode store configured to store microcode entries;

wherein any given one of said processor cores is further configured to;

generate a given microcode entrypoint corresponding to a particular microcode entry including one or more operations to be executed by said given processor core;

determine whether said particular microcode entry is stored within said respective local microcode unit of said given processor core; and

in response to determining that said particular microcode entry is not stored within said respective local microcode unit, convey a request for said particular microcode entry to said remote microcode unit.

2. The processor as recited in claim 1, wherein to determine whether said particular microcode entry is stored within said respective local microcode unit of said given processor core, said given processor core is further configured to determine whether said given microcode entrypoint is located in a portion of a microcode entrypoint address space corresponding to said respective local microcode unit.

3. The processor as recited in claim 1, wherein in response to receiving said request, said remote microcode unit is further configured to retrieve said particular microcode entry from said remote microcode store and to return said particular microcode entry to said given processor core.

4. The processor as recited in claim 3, wherein said particular microcode entry includes a sequence control field configured to indicate whether another microcode entry is to be retrieved subsequent to said particular microcode entry, and wherein said remote microcode unit is further configured, dependent on said sequence control field, to retrieve said another microcode entry from said remote microcode store and to return said another microcode entry to said given processor core without said given processor core separately requesting said another microcode entry.

5. The processor as recited in claim 1, wherein said given processor core is further configured to generate said given microcode entrypoint in response to decoding a given one of said instructions and determining that said given instruction is a microcoded instruction.

6. The processor as recited in claim 1, wherein said given processor core is further configured to generate said given microcode entrypoint in response to detecting an architecturally-defined processor event corresponding to a microcode routine.

7. The processor as recited in claim 1, wherein each of said processor cores further includes a respective instruction cache configured to store ones of said instructions, wherein in response to receiving said particular microcode entry subsequent to said request, said given processor core is further configured to store said particular microcode entry within said respective instruction cache.

8. The processor as recited in claim 1, wherein at least a portion of said remote microcode store includes writeable memory.

9. The processor as recited in claim 1, wherein microcode routines corresponding to microcode entries stored within said local microcode units each satisfy a performance sensitivity threshold requirement, while at least some microcode routines corresponding to microcode entries stored within said remote microcode unit each do not satisfy said performance sensitivity threshold requirement.

10. The processor as recited in claim 9, wherein said performance sensitivity threshold requirement is dependent upon a frequency of microcode routine execution.

11. The processor as recited in claim 9, wherein said performance sensitivity threshold requirement is dependent upon a latency of microcode routine execution.

12. A method, comprising:

a given one of a plurality of processor cores generating a given microcode entrypoint corresponding to a particular microcode entry including one or more operations to be executed by said given processor core, wherein each of said plurality of processor cores is configured to independently execute instructions defined according to a programmer-visible instruction set architecture (ISA), and wherein each of said plurality of processor cores includes a respective local microcode unit configured to store microcode entries;

said given processor core determining whether said particular microcode entry is stored within said respective local microcode unit of said given processor core; and

in response to determining that said particular microcode entry is not stored within said respective local microcode unit, said given processor core conveying a request for said particular microcode entry to a remote microcode unit, wherein said remote microcode unit is accessible by each of said processor cores and includes a remote microcode store configured to store microcode entries.

13. The method as recited in claim 12, wherein said given processor core determining whether said particular microcode entry is stored within said respective local microcode unit of said given processor core comprises said given processor core determining whether said given microcode entrypoint is located in a portion of a microcode entrypoint address space corresponding to said respective local microcode unit.

14. The method as recited in claim 12, further comprising:

in response to receiving said request, said remote microcode unit retrieving said particular microcode entry from said remote microcode store and returning said particular microcode entry to said given processor core.

15. The method as recited in claim 14, wherein said particular microcode entry includes a sequence control field configured to indicate whether another microcode entry is to be retrieved subsequent to said particular microcode entry, and wherein the method further comprises said remote microcode unit retrieving, dependent on said sequence control field, said another microcode entry from said remote microcode store and returning said another microcode entry to said given processor core without said given processor core separately requesting said another microcode entry.

16. The method as recited in claim 12, further comprising said given processor core generating said given microcode entrypoint in response to decoding a given one of said instructions and determining that said given instruction is a microcoded instruction.

17. The method as recited in claim 12, further comprising said given processor core generating said given microcode entrypoint in response to detecting an architecturally-defined processor event corresponding to a microcode routine.

18. The method as recited in claim 12, wherein each of said processor cores further includes a respective instruction cache configured to store ones of said instructions, and wherein the method further comprises said given processor core storing said particular microcode entry within said respective instruction cache in response to receiving said particular microcode entry subsequent to said request.

19. The method as recited in claim 12, wherein at least a portion of said remote microcode store includes writeable memory.

20. A system, comprising:

a system memory; and

a processor coupled to said system memory, wherein said processor comprises;

a plurality of processor cores, each configured to independently execute instructions defined according to a programmer-visible instruction set architecture (ISA), wherein each of said plurality of processor cores includes a respective local microcode unit configured to store microcode entries; and

a remote microcode unit accessible by each of said processor cores and including a remote microcode store configured to store microcode entries;

wherein any given one of said processor cores is further configured to;

generate a given microcode entrypoint corresponding to a particular microcode entry including one or more operations to be executed by said given processor core;

determine whether said particular microcode entry is stored within said respective local microcode unit of said given processor core; and

in response to determining that said particular microcode entry is not stored within said respective local microcode unit, convey a request for said particular microcode entry to said remote microcode unit.