STRUCTURE AND METHOD TO OPTIMIZE COMPUTATIONAL EFFICIENCY IN LOW-POWER ENVIRONMENTS

• US 20090024859A1
• Filed: 10/11/2007
• Published: 01/22/2009
• Est. Priority Date: 07/18/2007
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: GOODNOW, Kenneth J, Ventrone, Sebastian T., Ogilvie, Clarence R., Woodruff, Charles S., Williams, Keith
• Granted Patent: US 8,122,273 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

A method and structure to optimize computational efficiency in a low-power environment. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a component to determine an optimal point for maximizing computational efficiency in a low-power environment, and a component to selectively control operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point. The design structure further includes at least one of a component for controlling a frequency of a clock signal transmitted to the at least one processing unit in accordance with the determined optimal point, and a component for determining a present power available.

Claims

1. A design structure embodied in a computer readable medium for performing a method, the design structure comprising:

a means for determining an optimal point for maximizing computational efficiency in a low-power environment; and

a means for selectively controlling operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point.

2. The design structure of claim 1, wherein the design structure comprises a netlist, which describes the circuit.

3. The design structure of claim 1, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

4. The design structure of claim 1, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.

5. A design structure embodied in a machine readable medium used in a design process, the design structure comprising:

a component to determine an optimal point for maximizing computational efficiency in a low-power environment;

a component to selectively control operation of at least one processing unit of a plurality of processing units in accordance with the determined optimal point; and

at least one of;

(i) a component for controlling a frequency of a clock signal transmitted to the at least one processing unit in accordance with the determined optimal point, and (ii) a component for determining a present power available.