CIRCUIT ARRANGEMENT, DATA PROCESSING DEVICE COMPRISING SUCH CIRCUIT ARRANGEMENT AS WELL AS METHOD FOR IDENTIFYING AN ATTACK ON SUCH CIRCUIT ARRANGEMENT

• US 20090024890A1
• Filed: 02/05/2007
• Published: 01/22/2009
• Est. Priority Date: 02/09/2006
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Cutrignelli, Giancarlo, Malzahn, Ralf
• Application Number:
  US12/162,832
• Publication Number:
  US 20090024890A1
• Time in Patent Office: Days
• US Class Current: 714/736
• CPC Class Codes: G06F 21/87 by means of encapsulation, e.g. for integrated circuits
• CPC Class Codes: G06K 19/07363 by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
• CPC Class Codes: H01L 23/576 using active circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In order to further develop a circuit arrangement (100), in particular an active shield, as well as a method for identifying at least one attack on the circuit arrangement (100), wherein test data are generated, the test data are transmitted via at least one group of data lines (50) being designed for carrying data signals in the form of regular data and/or in the form of the test data, the transmitted test data are received, the received test data are compared with expected test data, and any discrepancy between the received test data and the expected test data is ascertained or determined, in such way that less power is required for examining, in particular for identifying, if the circuit arrangement (100) has been attacked, it is proposed that part of the group of data lines (50) is selected to carry new or most recent test data having been generated.

Claims

1. A circuit arrangement, in particular an active shield, comprising

at least one data signal generating device being designed for generating test data and expected test data,

at least one group of data lines being designed for carrying data signals, in particular regular data and/or the test data, and

at least one detector module being designed for identifying at least one attack on the circuit arrangement, the detector module comprising

at least one transmitting device for transmitting the test data,

at least one receiving device for receiving the test data having been transmitted from the transmitting device and

at least one evaluation device for comparing the received test data with the expected test data and for ascertaining or determining any discrepancy between the received test data and the expected test data,

characterized by

at least one data line selection device for selecting part of the group of data lines to carry new or most recent test data having been generated by the data signal generating device.

2. The circuit arrangement according to claim 1, characterized by at least one data line enabling device for enabling and disabling the selected part of the group of data lines to carry the new or most recent test data.

3. The circuit arrangement according claim 1, characterized in that the data signal generating device

generates the test data dynamically and/or randomly, in particular by means of at least one random number generating device, and

is connected

with the data line selection device, and/or

with the data line enabling device, and/or

with the transmitting device, and/or

with the evaluation device, and/or

with the random number generating device.

4. The circuit arrangement according to at least one of claims 1 to 3, characterized in that the group of data

is arranged in an upper plane of the circuit arrangement,

is situated at least in part above at least one security-critical circuit component being arranged in a lower plane of the circuit arrangement, said security-critical circuit component in particular comprising the detector module, the random number generating device, the data line selection device, the data line enabling device and the data signal generating device, and

is connected the security-critical circuit component.

5. A microcontroller, in particular an embedded security controller, comprising at least one circuit arrangement according to at least one of claims 1 to 4.

6. A data processing device, in particular an embedded system, for example a chip card or a smart card, comprising at least one circuit arrangement according to claim 1.

11. Use of at least one circuit arrangement, in particular of at least one active shield, according to at least one of claims 1 to 4 and/or of the method according to claim 7 for protecting at least one integrated circuit against at least one attack, wherein the integrated circuit can be arranged in at least one data processing device, in particular in at least one embedded system, for example in at least one chip card or smart card, according to claim 6 in the field of public key cryptography, such as banking, online shopping, PayT[ele]V[ision], security, etc.

7. A method for identifying at least one attack on at least one circuit arrangement, in particular on at least one active shield, wherein

test data are generated,

the test data are transmitted via at least one group of data lines being designed for carrying data signals in the form of regular data and/or in the form of the test data,

the transmitted test data are received,

the received test data are compared with expected test data, and

any discrepancy between the received test data and the expected test data is ascertained or determined,

characterized in

that part of the group of data lines is selected to carry new or most recent test data having been generated.

8. The method according to claim 7, characterized in that the selected part of the group of data lines is enabled or disabled to carry the new or most recent test data wherein the data lines of the selected part of the group of data lines can be enabled preferably simultaneously and/or can be disabled preferably simultaneously.

9. The method according to claim 8, characterized in that

upon enabling one or several data lines having been selected, said at least one enabled data line switches from carrying at least one first kind of the data signals, in particular the regular data or older test data, to carrying the new or most recent test data, and

upon disabling one or several data lines having been selected, said at least one disabled data line switches from carrying the new or most recent test data to carrying the first kind of the data signals, in particular the regular data.

10. A computer program product directly loadable into the memory of at least one computer, comprising at least one software code portion for performing the method according to claim 7 when said computer program product is run on the computer, said computer program being in particular electronically distributable.