COMBINED DISTORTION ESTIMATION AND ERROR CORRECTION CODING FOR MEMORY DEVICES

• US 20090024905A1
• Filed: 05/10/2007
• Published: 01/22/2009
• Est. Priority Date: 05/12/2006
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Shalvi, Ofir, Sokolov, Dotan, Sommer, Naftali, Maislos, Ariel
• Granted Patent: US 8,156,403 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1072 in multilevel memories

Abstract

A method for operating a memory device (24) includes encoding data using an Error Correction Code (ECC) and storing the encoded data as first analog values in respective analog memory cells (32) of the memory device. After storing the encoded data, second analog values are read from the respective memory cells of the memory device in which the encoded data were stored. At least some of the second analog values differ from the respective first analog values. A distortion that is present in the second analog values is estimated. Error correction metrics are computed with respect to the second analog values responsively to the estimated distortion. The second analog values are processed using the error correction metrics in an ECC decoding process, so as to reconstruct the data.

Claims

1. A method for operating a memory device, comprising:

encoding data using an Error Correction Code (ECC) and storing the encoded data as first analog values in respective analog memory cells of the memory device;

after storing the encoded data, reading from the memory cells of the memory device in which the encoded data were stored respective second analog values, at least some of which differ from the respective first analog values;

estimating a distortion that is present in the second analog values;

computing error correction metrics with respect to the second analog values responsively to the estimated distortion; and

processing the second analog values using the error correction metrics in an ECC decoding process, so as to reconstruct the data.

2. The method according to claim 1, wherein computing the error correction metrics comprises evaluating, for each memory cell, one or more cell parameters indicative of the distortion, and computing the error correction metrics responsively to the cell parameters.

3. The method according to claim 2, wherein the cell parameters comprise at least one parameter selected from a group of parameters consisting of the analog values read from other memory cells, estimated cross-coupling coefficients of the other memory cells, parameters of a statistical distribution of the read second analog values, a number of previous programming and erasure cycles the memory cell has gone through, time durations that elapsed since the previous programming and erasure cycles, previous errors detected in the memory cell, an identity of a word line to which the memory cell is connected, an identity of a bit line to which the memory cell is connected, an estimated parameter of a sense amplifier coupled to the bit line to which the memory cell is connected and an environmental parameter.

4. The method according to claim 1, wherein processing the second analog values comprises dividing a range of possible values of the second analog values into multiple decision intervals and determining the respective decision intervals in which the second analog values fall, and wherein computing the error correction metrics comprises defining a function that modifies the second analog values relative to the decision intervals, so as to improve a performance of the ECC decoding process.

5. The method according to claim 1, wherein processing the second analog values comprises accepting feedback regarding a performance of the ECC decoding process, and modifying the ECC decoding process responsively to the feedback.

6. The method according to claim 1, wherein processing the second analog values comprises comparing the second analog values to decision thresholds, and wherein modifying the ECC decoding process comprises modifying the decision thresholds.

7. The method according to claim 6, wherein modifying the decision thresholds comprises re-reading the second analog values from the memory cells using the modified decision thresholds.

8. The method according to claim 6, wherein comparing the second analog values to the decision thresholds comprises reading the second analog values at the memory device using the decision thresholds, and wherein modifying the decision thresholds comprises sending a command to the memory device requesting to modify the thresholds.

9. The method according to claim 6, wherein processing the second analog values comprises producing multiple estimates of the data stored in each memory cell by performing respective multiple iterations of the ECC decoding process using different sets of the decision thresholds, and reconstructing the data responsively to the multiple estimates of the data.

10. The method according to claim 9, wherein reconstructing the data comprises selecting one of the multiple estimates independently for each memory cell.

11. The method according to claim 5, wherein processing the second analog values comprises applying a first ECC decoding process having a first error performance, wherein accepting the feedback comprises accepting an indication of decoding errors in the data decoded using the first process, and wherein modifying the ECC decoding process comprises processing the second analog values using a second ECC decoding process having a second error performance better than the first error performance.

12. The method according to claim 5, wherein modifying the ECC decoding process comprises modifying a sampling resolution used in reading the second analog values.

13. The method according to claim 1, wherein reading the second analog values comprises reading multiple instances of the second analog values using respective different sets of decision thresholds, and wherein computing the error correcting metrics comprises combining the multiple instances independently for each memory cell and computing the error correcting metrics based on the combined multiple instances.

14. The method according to claim 13, wherein reading and combining the multiple instances of the second analog values comprise iteratively obtaining additional instances of the second analog values and updating the error correcting metrics using the additional instances until successfully decoding the ECC.

15. The method according to claim 1, wherein for each memory cell, estimating the distortion comprises reading the second analog values from a subset of potentially-interfering memory cells that potentially contribute to the distortion in the second analog value read from the memory cell, and wherein computing the error correction metrics comprises evaluating the distortion contributed by the potentially-interfering memory cells.

16. The method according to claim 15, wherein evaluating the distortion contributed by the potentially interfering memory cells to the memory cell comprises approximating the distortion contributed by each potentially-interfering memory cell based on both the second analog value read from the potentially-interfering memory cell and on the second analog value read from the memory cell.

17. The method according to claim 15, wherein processing the second analog values comprises processing the second analog value of the memory cell at a first quantization level, and processing the second analog values read from the potentially-interfering memory cells at a second quantization level that is coarser than the first quantization level.

18. The method according to claim 17, wherein processing the second analog values comprises reading the second analog values at the first and second quantization levels by iteratively modifying a threshold of a circuit used for reading the second analog values.

19. The method according to claim 1, wherein storing the encoded data comprises writing the first analog values into the memory cells using a Program and Verify (P&

V) process, and wherein estimating the distortion comprises classifying the potentially-interfering memory cells into at least two classes selected from a group of classes consisting of memory cells that were fully programmed earlier than the memory cell, memory cells that were fully programmed later than the memory cell and memory cells that were that were fully programmed concurrently with the memory cell by the P&

V process, and calculating the aggregate distortion separately within each of the classes.

20. The method according to claim 1, wherein the memory cells comprise Flash memory cells.

21. The method according to claim 1, wherein the memory cells comprise Dynamic Random Access Memory (DRAM) cells.

22. The method according to claim 1, wherein the memory cells comprise Phase Change Memory (PCM) cells.

23. The method according to claim 1, wherein the memory cells comprise Nitride Read-Only Memory (NROM) cells.

24. The method according to claim 1, wherein the memory cells comprise Magnetic Random Access Memory (MRAM) cells.

25. The method according to claim 1, wherein the memory cells comprise Ferroelectric Random Access Memory (FRAM) cells.

26. The method according to claim 1, wherein the ECC comprises a block code.

27. The method according to claim 26, wherein the block code comprises one of a Bose-ChaudhuriHochquenghem (BCH) code and a Reed-Solomon (RS) code.

28. The method according to claim 26, wherein the block code comprises one of a Low-Density Parity Check (LDPC) code, a turbo-code and a Turbo Product Code (TPC).

29. The method according to claim 28, wherein the ECC decoding process comprises an iterative decoding process.

30. The method according to claim 1, wherein the ECC decoding process uses feedback produced by reading the second analog values.

31. The method according to claim 1, wherein the ECC decoding process comprises a Maximum Likelihood Sequence Estimation (MLSE) process.

32. The method according to claim 1, wherein the ECC comprises one of a convolutional code, a Trellis-Coded Modulation (TCM) code, a Bit Interleaved Coded Modulation (BICM) code and a concatenated code.

33. The method according to claim 1, wherein the error correction metrics comprise Likelihood Ratios (LRs).

34. The method according to claim 1, wherein the error correction metrics comprise Log Likelihood Ratios (LLRs).

35. The method according to claim 1, wherein estimating the distortion comprises predicting the distortion present in one of the memory cells based on the distortion present In other memory cells.

36. The method according to claim 1, wherein the memory cells are arranged in isolated groups of potentially-interfering cells, wherein estimating the distortion in each group comprises evaluating an inverse of a cross-coupling matrix representing mutual interference between pairs of the memory cells in the group, and wherein computing the error correction metrics comprises computing a distance between the inverse of the cross-coupling matrix applied to the first analog values, summed with average distortion levels in the respective memory cells in the group, and the inverse of the cross-coupling matrix applied to the second analog values.

37. The method according to claim 36, wherein the isolated groups comprise respective Nitride Read-Only Memory (NROM) cells, and wherein the potentially interfering cells in each group comprise first and second charge storage areas of the respective NROM cell.

38. The method according to claim 1, wherein the memory cells are arranged in isolated groups of potentially-interfering cells, wherein estimating the distortion in each group comprises evaluating a vector of average distortion levels in the respective memory cells in the group and a croso-coupling matrix representing mutual interference between pairs of the memory cells in the group, and wherein computing the error correction metrics comprises computing the metrics responsively to a difference between a vector of the second analog values read from the memory cells in the group and a product of the cross-coupling matrix and the vector of the average distortion levels.

39. The method according to claim 38, wherein the isolated groups comprise respective Nitride Read-Only Memory (NROM) cells, and wherein the potentially interfering cells in each group comprise first and second charge storage areas of the respective NROM cell.

40. The method according claim 1, wherein storing the encoded data comprises scrambling the encoded data and storing the scrambled data, and wherein processing the second analog values comprises descrambling the second analog values read from the memory cells.

41. The method according to claim 1, wherein storing the data comprises maintaining at least some of the memory cells at an erased level, and wherein reading the second analog values, estimating the distortion, computing the error correcting metrics and processing the second analog values comprise compensating for the distortion in the second analog values read from the memory cells that were maintained at the erased level.

42. A method for operating a memory device, comprising:

storing data as first analog values in respective analog memory cells of the memory device;

after storing the data, reading multiple instances of second analog values from the respective memory cells, each of the instances read by comparing the second analog values to a respective decision threshold;

estimating a distortion that is present in the second analog values; and

processing the multiple instances of the second analog values responsively to the estimated distortion, so as to reconstruct the data.

43. The method according to claim 42, wherein reading and processing the multiple instances comprise iteratively obtaining additional instances of the second analog values.

44. Apparatus for retrieving data that has been encoded using an Error Correction Code (ECC) and stored as first analog values in respective analog memory cells of a memory device, the apparatus comprising:

a reading unit, which is arranged to read from the analog memory cells of the memory device in which the encoded data were stored respective second analog values, at least some of which differ from the respective first analog values;

a signal processing unit, which is arranged to estimate a distortion that is present in the second analog values and to compute error correction metrics with respect to the second analog values responsively to the estimated distortion; and

a decoder, which is arranged to process the second analog values using the error correction metrics, so as to decode the ECC and reconstruct the data.

45. The Apparatus according to claim 44 wherein the signal processing unit is arranged to evaluate, for each memory cell, one or more cell parameters indicative of the distortion, and to compute the error correction metrics responsively to the cell parameters.

46. The apparatus according to claim 45, wherein the cell parameters comprise at least one parameter selected from a group of parameters consisting of the second voltages read from other memory cells, estimated cross-coupling coefficients of the other memory cells, parameters of a statistical distribution of the read second analog values, a number of previous programming and erasure cycles the memory cell has gone through, time durations that elapsed since the previous programming and erasure cycles, previous errors detected in the memory cell, an identity of a word line to which the memory cell is connected, an identity of a bit line to which the memory cell is connected, an estimated parameter of a sense amplifier coupled to the bit line to which the memory cell is connected and an environmental parameter.

47. The apparatus according to claim 44, wherein the decoder is arranged to divide a range of possible values of the second analog values into multiple decision intervals and to determine the respective decision intervals in which the second analog values fall, and wherein the signal processing unit is arranged to define a function that modifies the second analog values relative to the decision intervals based on the estimated distortion, so as to improve a performance of the decoder.

48. The apparatus according to claim 44, wherein the signal processing unit is arranged to accept feedback regarding a performance of the decoder, and to modify an operation of the decoder responsively to the feedback.

49. The apparatus according to claim 44, wherein the decoder is arranged to compare the second analog values to decision thresholds, and wherein the signal processing unit is arranged to modify the operation of the decoder by modifying the decision thresholds responsively to the feedback.

50. The apparatus according to claim 49, wherein the reading unit is arranged to read the second analog values by comparing the second analog values to the decision thresholds, and wherein the signal processing unit is arranged to modify the decision thresholds by sending a command to the reading unit requesting to modify the thresholds.

51. The apparatus according to claim 49, wherein the signal processing unit is arranged to cause the reading unit to re-read the second analog values from the memory cells using the modified decision thresholds.

52. The apparatus according to claim 49, wherein the decoder is arranged to produce multiple estimates of the data stored in each memory cell by performing respective multiple decoding iterations using different sets of the decision thresholds, and to reconstruct the data responsively to the multiple estimates of the data.

53. The apparatus according to claim 52, wherein the decoder is arranged to reconstruct the data by selecting one of the multiple estimates independently for each memory cell.

54. The apparatus according to claim 48, wherein the decoder is arranged to initially apply a first ECC decoding process having a first error performance, wherein the signal processing unit is arranged to accept an indication of decoding errors in the data decoded using the first decoding process, and to cause the decoder to process the second analog values using a second ECC decoding process having a second error performance better than the first error performance.

55. The apparatus according to claim 48, wherein the signal processing unit is arranged to modify a sampling resolution used by the reading unit for reading the second analog values responsively to the feedback.

56. The apparatus according to claim 44, wherein the reading unit is arranged to read multiple instances of the second analog values using respective different sets of decision thresholds, wherein the signal processing unit is arranged to combine the multiple instances independently for each memory cell and to compute the error correcting metrics based on the combined multiple instances.

57. The apparatus according to claim 56, wherein the reading unit, the signal processing unit and the decoder are arranged to iteratively obtain additional instances of the second analog values and to update the error correcting metrics using the additional instances until successfully decoding the ECC.

58. The apparatus according to claim 44, wherein the reading unit is arranged, for each memory cell, to read the second analog values from a subset of potentially-interfering memory cells that potentially contribute to the distortion in the second analog value read from the memory cell, and wherein the signal processing unit is arranged to evaluate the distortion contributed by the potentially interfering memory cells.

59. The apparatus according to claim 58, wherein the signal processing unit is arranged to approximate the distortion contributed by each potentially-interfering memory cell based on both the second analog value read from the potentially-interfering memory cell and on the second analog value read from the memory cell.

60. The apparatus according to claim 58, wherein the signal processing unit is arranged to process the second analog value of the memory cell at a first quantization level, and to process the second analog values read from the potentially-interfering memory cells at a second quantization level that is coarser than the first quantization level.

61. The apparatus according to claim 60, wherein the reading unit is arranged to compare the second analog values to a threshold, and to iteratively modify the threshold so as to read the second analog values at the first and second quantization levels.

62. The apparatus according to claim 44, wherein the first analog values were written into the memory cells using a Program and Verify (P&

V) process, and wherein the signal processing unit is arranged to classify the potentially-interfering memory cells into at least two classes selected from a group of classes consisting of memory cells that were fully programmed earlier than the memory cell, memory cells that were fully programmed later than the memory cell and memory cells that were fully programmed concurrently with the memory cell by the P&

V process, and to calculate the aggregate distortion separately within each of the classes.

63. The apparatus according to claim 44, wherein the reading unit resides in a first Integrated Circuit (IC) and wherein the signal processing unit and the decoder reside in a second IC different from the first IC.

64. The apparatus according to claim 44, wherein the reading unit, the signal processing unit and the decoder are integrated in a single device.

65. The apparatus according to claim 44, wherein the memory cells comprise Flash memory cells.

66. The apparatus according to claim 44, wherein the memory cells comprise Dynamic Random Access Memory (DRAM) cells.

67. The apparatus according to claim 44, wherein the memory cells comprise Phase Change Memory (PCM) cells.

68. The apparatus according to claim 44, wherein the memory cells comprise Nitride Read-Only Memory (NROM) cells.

69. The apparatus according to claim 44, wherein the memory cells comprise Magnetic Random Access Memory (MRAM) cells.

70. The apparatus according to claim 44, wherein the memory cells comprise Ferroelectric Random Access Memory (FRAM) cells.

71. The apparatus according to claim 44, wherein the ECC comprises a block code.

72. The apparatus according to claim 71, wherein the block code comprises one of a Bose-ChaudhuriHochquenghem (BCH) code and a Reed-Solomon (RS) code.

73. The apparatus according to claim 71, wherein the ECC comprises one of a Low-Density Parity Check (LDPC) code, a turbo-code and a Turbo Product Code (TPC).

74. The apparatus according to claim 73, wherein the decoder is arranged to decode the ECC using an iterative decoding process.

75. The apparatus according to claim 44, wherein the decoder is arranged to decode the ECC using feedback that is produced by reading the second analog values.

76. The apparatus according to claim 44, wherein the decoder is arranged to decode the ECC using a Maximum Likelihood Sequence Estimation (MLSE) process.

77. The apparatus according to claim 44, wherein the ECC comprises one of a convolutional code, a Trellis-Coded Modulation (TCM) code, a Bit Interleaved Coded Modulation (BICM) code and concatenated code.

78. The apparatus according to claim 44, wherein the error correction metrics comprise Likelihood Ratios (LRs).

79. The apparatus according to claim 44, wherein the error correction metrics comprise Log Likelihood Ratios (LLRs).

80. The apparatus according to claim 44, wherein the signal processing unit is arranged to predict the distortion present in one of the memory cells based on the distortion present in other memory cells.

81. The apparatus according to claim 44, wherein the memory cells are arranged in isolated groups of potentially-interfering cells, and wherein the signal processing unit is arranged to estimate the distortion in each group by evaluating an inverse of a cross-coupling matrix representing mutual interference between pairs of the memory cells in the group, and wherein computing the error correction metrics comprises computing a distance between the inverse of the cross-coupling matrix applied to the first analog values, summed with average distortion levels in the respective memory cells in the group, and the inverse of the cross-coupling matrix applied to the second analog values.

82. The apparatus according to claim 81, wherein the isolated groups comprise respective Nitride Read-Only Memory (NROM) cells, and wherein the potentially-interfering cells in each group comprise first and second charge storage areas of the respective NROM cell.

83. The apparatus according to claim 44, wherein the memory cells are arranged in isolated groups of potentially-interfering cells, and wherein the signal processing unit is arranged to estimate the distortion in each group by evaluating a vector of average distortion levels in the respective memory cells in the group and a cross-coupling matrix representing mutual interference between pairs of the memory cells in the group, and to compute the error correction metrics responsively to a difference between a vector of the second analog values read from the memory cells in the group and a product of the cross-coupling matrix and the vector of the average distortion levels.

84. The apparatus according to claim 83, wherein the isolated groups comprise respective Nitride Read-Only Memory (NROM) cells, and wherein the potentially-interfering cells in each group comprise first and second charge storage areas of the respective NROM cell.

85. The apparatus according to claim 44, wherein the data stored in the memory cells is scrambled, and wherein the signal processing unit is arranged to descramble the second analog values read from the memory cells.

86. The apparatus according to claim 44, wherein at least some of the memory cells are maintained at an erased level, and wherein the signal processing unit is arranged to compensate for the distortion in the second analog values read from the memory cells that were maintained at the erased level.

88. The apparatus according to claim 77, wherein the reading unit and the signal processing unit are arranged to iteratively obtain additional instances of the second analog values.

87. Apparatus for retrieving data that has been stored as first analog values in respective analog memory cells of a memory device, the apparatus comprising:

a reading unit, which is arranged to read multiple instances of second analog values from the respective memory cells, each of the instances read by comparing the second analog values to a respective decision threshold; and

a signal processing unit, which is arranged to estimate a distortion that is present in the second analog values and to process the multiple instances of the second analog values responsively to the estimated distortion, so as to reconstruct the data.