CRC SYNDROME GENERATION FOR MULTIPLE DATA INPUT WIDTHS

• US 20090024907A1
• Filed: 07/17/2007
• Published: 01/22/2009
• Est. Priority Date: 07/17/2007
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: RICHARD, ELIZABETH ANNE
• Granted Patent: US 8,015,476 B2
• Time in Patent Office: Days
• US Class Current: 714/796
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Abstract

A sequence of cyclic redundancy check syndromes can be produced based on a received sequence of sets of parallel data wherein different ones of the sets can have respectively different parallel data widths. Some of the syndromes are produced based on respectively corresponding ones of the sets that each have a first parallel data width. At least one of the syndromes is produced based on a corresponding at least one of the sets that has a second parallel data width that is less than the first parallel data width. The last syndrome of the sequence of syndromes corresponds to all of the data in the received sequence of sets.

Claims

1. A cyclic redundancy check apparatus, comprising:

a data input for receiving a sequence of sets of parallel data, each of said sets having a parallel data width that is at least as large as a first width and no larger than a second width that exceeds said first width; and

a next state decoding portion coupled to said data input for producing a sequence of syndromes based on said received sequence of sets, said next state decoding portion configured to produce some of said syndromes based on respectively corresponding ones of said sets that have respective parallel data widths that are equal to said second width, and said next state decoding portion further configured to produce at least one of said syndromes based on a corresponding at least one of said sets that has a parallel data width that is less than said second width;

wherein a last syndrome of said sequence of syndromes corresponds to all of said data in said sequence of sets.

2. The apparatus of claim 1, wherein said next state decoding portion includes a control input for receiving a control signal that indicates when said at least one syndrome is to be produced.

3. The apparatus of claim 2, wherein said next state decoding portion includes a first next state decoder configured to produce said some syndromes, and a second next state decoder configured to produce said at least one syndrome, each of said first and second next state decoders having a syndrome input and a syndrome output, and wherein said next state decoding portion includes a feedback path, coupled to said syndrome outputs and said, syndrome inputs.

4. The apparatus of claim 3, wherein said next state decoding portion, includes a selector coupled to said control input and responsive to said control signal for coupling a selected one of said syndrome outputs to said feedback path.

5. The apparatus of claim 3, wherein said syndrome inputs are connected to one another.

6. The apparatus of claim 3, wherein said feedback path includes a register.

7. The apparatus of claim 3, wherein said parallel data width that is less than said second width is equal to said first width, wherein said next state decoding portion includes a third next state decoder for producing at least another of said syndromes based on a corresponding at least another of said sets that has a parallel data width that is between said first width and said second width, and wherein said third, next state decoder has a syndrome input and a syndrome output that are coupled to said feedback path.

8. The apparatus of claim 7, wherein said second width is equal to a sum of said first width and said between width.

9. The apparatus of claim 1, including a monitor configured to monitor a control signal associated with said received sequence of sets, said next state decoding portion coupled to said monitor, said monitor and said next state decoding portion cooperable in response to said control signal for configuring said next state decoding portion to produce said at least one syndrome.

10. The apparatus of claim 9, wherein said next state decoding portion includes a first next state decoder configured to produce said some syndromes, a second next state decoder configured to produce said at least one syndrome, and a selector having an output, and having first and second inputs coupled to said data input, and wherein said second next state decoder has a data input coupled to said selector output.

11. The apparatus of claim 10, wherein said selector includes a control input, that receives said control signal.

12. The apparatus of claim 11, wherein each of said first and second next state decoders has a syndrome input and a syndrome output, wherein said next state decoding portion includes a feedback path coupled to said syndrome outputs and said syndrome inputs, and wherein said next state decoding portion includes a further selector coupled to said monitor and cooperable therewith in response to said control signal for coupling a selected one of said syndrome outputs to said feedback path.

13. The apparatus of claim 9, wherein said next state decoding portion includes a first next state decoder configured to produce said some syndromes, and a second next, state decoder configured to produce said at least one syndrome, each of said first and second next state decoders having a syndrome input and a syndrome output, wherein said next state decoding portion includes a feedback path coupled to said syndrome outputs and said syndrome inputs, and wherein said next state decoding portion includes a selector coupled to said monitor and cooperable therewith in response to said control signal for coupling a selected one of said syndrome outputs to said, feedback path.

14. The apparatus of claim 9, wherein said monitor includes an AND gate having an input that receives said control signal, and having an output coupled to said next state decoding portion.

15. The apparatus of claim 1, wherein said first width is equal to one-half of said second width.

16. A cyclic redundancy check method, comprising:

receiving a sequence of sets of parallel data, each of said sets having a parallel data width that is at least as large as a first width and no larger than a second width that exceeds said first width; and

producing a sequence of syndromes based on said received sequence of sets, including producing some of said syndromes based on respectively corresponding ones of said sets that have respective parallel data widths that are equal to said second width, and producing at least one of said syndromes based on a corresponding at least one of said sets that has a parallel data width that is less than said second width;

wherein a last syndrome of said sequence of syndromes corresponds to all of said data in said sequence of sets.

17. The method of claim 16, wherein said parallel data width that is less than said second width is equal to said first width, and including producing at least another of said syndromes based on a corresponding one of said sets that has a parallel data width that is between said first width and said second width.

18. The method of claim 17, wherein said second width is equal to a sum of said first width and said between width.

19. The method of claim 16, wherein said first width is equal to one-half of said second width.

20. The method of claim 16, including monitoring a control signal associated with said received sequence of sets to determine when to produce said at least one syndrome.