Semiconductor Device and Method of Manufacturing Semiconductor Device

• US 20090026504A1
• Filed: 12/21/2006
• Published: 01/29/2009
• Est. Priority Date: 12/27/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Wakabayashi, Hitoshi, Okuda, Yoshifumi
• Granted Patent: US 7,723,808 B2
• Time in Patent Office: Days
• US Class Current: 257/255
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

The present invention provides a semiconductor device and a method of manufacturing a semiconductor device in which a driving force can be increased by increasing a strain amount given by a stressed film in a MOS transistor including an elevated region.

On a silicon substrate, a device isolation region 102, a gate insulating film 103, a gate electrode 104, an extension 105, and a sidewall insulating film 106 are formed. After that, an elevated region is formed, and a source/drain region 108 and a silicide layer 109 are formed. Subsequently, the sidewall insulating film 106 is etched to provide a gap from the elevated region 107, and a stressed film 110 is buried in the gap.

Claims

1. A semiconductor device comprising:

a gate insulating film formed on a main plane of a semiconductor substrate;

a gate electrode formed on the gate insulating film;

a sidewall insulating film formed on side planes of the gate electrode;

a source/drain region formed while sandwiching the gate electrode;

an elevated region in which the source/drain region extends upward from the main plane of the semiconductor substrate while sandwiching the gate electrode and the sidewall insulating film; and

a stressed film including the gate electrode and the sidewall insulating film and extending to a position adjacent to the elevated region,

wherein the sidewall insulating film and the elevated region are not in contact with each other but a gap is provided therebetween, and the stressed film is buried in the gap.

3. The semiconductor device according to claim 1, wherein any of single crystals of silicon, germanium, and carbon or mixed crystal thereof is buried in the source/drain region.

4. The semiconductor device according to claim 1, wherein a semiconductor thin layer for forming the elevated region is made of any of single crystals of silicon, germanium, and carbon or mixed crystal thereof, and includes a single-layer or multilayer structure of the crystal(s).

5. The semiconductor device according to claim 1, wherein an end of the elevated region includes a single facet plane or a plurality of facet planes.

6. The semiconductor device according to claim 5, wherein a main plane of the semiconductor substrate is a (100) plane, a channel direction of the gate electrode is <

110>

, and the facet plane is a (111) plane, a (311) plane or a (511) plane, or includes a plane direction equivalent to any of these planes.

7. The semiconductor device according to claim 5, wherein a main plane of the semiconductor substrate is a (100) plane, a channel direction of the gate electrode is <

100>

, and the facet plane is a (110) plane, a (310) plane or a (510) plane, or includes a plane direction equivalent to any of these planes.

16. The semiconductor device according to claim 3, wherein a semiconductor thin layer for forming the elevated region is made of any of single crystals of silicon, germanium, and carbon or mixed crystal thereof, and includes a single-layer or multilayer structure of the crystal(s).

18. The semiconductor device according to claim 3, wherein an end of the elevated region includes a single facet plane or a plurality of facet planes.

19. The semiconductor device according to claim 4, wherein an end of the elevated region includes a single facet plane or a plurality of facet planes.

2. A semiconductor device comprising:

a gate insulating film formed on a main plane of a semiconductor substrate;

a gate electrode formed on the gate insulating film;

a source/drain region formed while sandwiching the gate electrode;

an elevated region in which the source/drain region extends upward from the main plane of the semiconductor substrate while sandwiching the gate electrode; and

a stressed film including the gate electrode and extending to a position adjacent to the elevated region,

wherein the gate electrode and the elevated region are not in contact with each other but a gap is provided therebetween, and the stressed film is buried in the gap.

14. The semiconductor device according to claim 2, wherein any of single crystals of silicon, germanium, and carbon or mixed crystal thereof is buried in the source/drain region.

15. The semiconductor device according to claim 2, wherein a semiconductor thin layer for forming the elevated region is made of any of single crystals of silicon, germanium, and carbon or mixed crystal thereof, and includes a single-layer or multilayer structure of the crystal(s).

17. The semiconductor device according to claim 2, wherein an end of the elevated region includes a single facet plane or a plurality of facet planes.

8. A method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a main plane of a semiconductor substrate;

forming a gate electrode on the gate insulating film;

forming a sidewall insulating film on side planes of the gate electrode;

forming a source/drain region while sandwiching the gate electrode;

forming an elevated region in which the source/drain region extends upward from the main plane of the semiconductor substrate while sandwiching the gate electrode and the sidewall insulating film;

forming a gap between the sidewall insulating film and the elevated region; and

burying a stressed film in the gap.

9. The method of manufacturing a semiconductor device according to claim 8, wherein any of single crystals of silicon, germanium, and carbon or mixed crystal thereof is buried in formation of the source/drain region.

10. The method of manufacturing a semiconductor device according to claim 8, wherein a semiconductor thin layer is made of any of single crystals of silicon, germanium, and carbon or mixed crystal thereof, and the elevated region is formed so as to include a single-layer or multilayer structure of the crystal(s).

11. The method of manufacturing a semiconductor device according to claim 8, wherein an end of the elevated region includes a single facet plane or a plurality of facet planes. 11, wherein a main plane of the semiconductor substrate is a (100) plane, a channel direction of the gate electrode is <

110>

, and the facet plane is a (111) plane, a (311) plane or a (511) plane, or includes a plane direction equivalent to any of these planes.

13. The method of manufacturing a semiconductor device according to claim 11, wherein a main plane of the semiconductor substrate is a (100) plane, a channel direction of the gate electrode is <

100>

, and the facet plane is a (110) plane, a (310) plane or a (510) plane, or includes a plane direction equivalent to any of these planes.

20. The method of manufacturing a semiconductor device according to claim 9, wherein a semiconductor thin layer is made of any of single crystals of silicon, germanium, and carbon or mixed crystal thereof, and the elevated region is formed so as to include a single-layer or multilayer structure of the crystal(s).