SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

• US 20090026505A1
• Filed: 07/25/2008
• Published: 01/29/2009
• Est. Priority Date: 07/27/2007
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: OKANO, Kimitoshi
• Granted Patent: US 7,915,693 B2
• Time in Patent Office: Days
• US Class Current: 257/255
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A semiconductor device according to an embodiment includes: a semiconductor substrate; a fin formed on the semiconductor substrate; a gate electrode formed so as to sandwich both side faces of the fin between its opposite portions via a gate insulating film; an extension layer formed on a region of a side face of the fin, the region being on the both sides of the gate electrode, the extension layer having a plane faced to a surface of the semiconductor substrate at an acute angle; and a silicide layer formed on a surface of the plane faced to the surface of the semiconductor substrate at an acute angle.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a fin formed on the semiconductor substrate;

a gate electrode formed so as to sandwich both side faces of the fin between its opposite portions via a gate insulating film;

an extension layer formed on a region of a side face of the fin, the region being on the both sides of the gate electrode, the extension layer having a plane faced to a surface of the semiconductor substrate at an acute angle; and

a silicide layer formed on a surface of the plane faced to the surface of the semiconductor substrate at an acute angle.

2. A semiconductor device according to claim 1, wherein the gate electrode has gate silicide layers on upper and lower sides thereof.

3. A semiconductor device according to claim 1, wherein a strain generating film to generate a strain in a region of the fin is formed under the gate electrode, the region being sandwiched by opposite portions of the gate electrode.

4. A semiconductor device according to claim 1, wherein the extension layer comprises a Si-based crystal.

5. A semiconductor device according to claim 1, wherein the plane faced to the surface of the semiconductor substrate at an acute angle is a facet of which plane direction is {111}.

6. A semiconductor device according to claim 1, wherein the extension layer has a plane facing to a height direction of the fin and forming an acute angle with a surface of the semiconductor substrate.

7. A method of fabricating a semiconductor device, comprising:

forming an insulating film on a semiconductor substrate on which fin is fabricated, so as to cover at least a portion of a side face of the fin;

forming a trench having an opening on an upper side thereof in a region of the insulating film by processing the insulating film, the region being adjacent to the fin;

forming a gate electrode on the insulating film in which the trench has been formed, so as to sandwich the both sides of the fin between its opposite portions via a gate insulating film;

forming an extension layer by epitaxially growing a crystal using a side face of the fin as a base after forming the gate electrode to substantially block off the opening of the trench of the insulating film;

lowering the height of the insulating film after forming the extension layer; and

forming a silicide layer on a surface of the extension layer after lowering the height of the insulating film.

8. The method of fabricating a semiconductor device according to claim 7, wherein a gate sidewall is formed on a side face of a gate electrode after forming the extension layer;

and

the height of the insulating film is lowered after forming the gate sidewall.

9. The method of fabricating a semiconductor device according to claim 7, wherein the upper surface of the insulating film is located below the upper surface of the fin at the time the trench is formed.

10. The method of fabricating a semiconductor device according to claim 7, wherein the extension layer is formed by epitaxially growing the crystal so as to contact with the insulating film.

11. The method of fabricating a semiconductor device according to claim 7, wherein the extension layer is formed by epitaxially growing a Si-based crystal.

12. The method of fabricating a semiconductor device according to claim 7, wherein the extension layer has a facet faced to the surface of the semiconductor substrate at an acute angle.

13. The method of fabricating a semiconductor device according to claim 12, wherein a plane direction of the facet is {111}.

14. The method of fabricating a semiconductor device according to claim 7, wherein a cap layer is formed on the fin before forming the insulating film;

the insulating film is formed so as to cover a side face of the fin and at least a portion of a side face of the cap layer;

the height of the cap layer is lowered below the height of a portion of the insulating film, the portion being adjacent to the cap layer; and

the trench is formed by providing a slant at a portion from the upper surface of the insulating film to a predetermined depth after lowering the height of the cap layer, the slant being provided by etching back the insulating film.

15. The method of fabricating a semiconductor device according to claim 14, wherein the extension layer has a facet which substantially matches the slant of the insulating film.

16. The method of fabricating a semiconductor device according to claim 7, wherein a strain generating film to generate a strain in a region of the fin is formed on the whole surface on the semiconductor substrate after forming the silicide layer, the region being sandwiched by opposite portions of the gate electrodes.

17. The method of fabricating a semiconductor device according to claim 16, wherein the strain generating film is formed in a gap, the gap being formed under the gate electrode by lowering the height of the insulating film.

18. The method of fabricating a semiconductor device according to claim 7, wherein the lower surface of the gate electrode is exposed by lowering the height of the insulating layer;

and

silicide layers are formed on the surface of the extension layer and the lower and upper surfaces of the gate electrode after exposing the lower surface of the gate electrode.

19. The method of fabricating a semiconductor device according to claim 7, wherein a volume of the extension layer is increased by epitaxially growing another crystal using a surface of the extension layer as a base after lowering the height of the insulating film;

and

the silicide layer is formed on a surface of the extension layer whose volume has been increased.

20. The method of fabricating a semiconductor device according to claim 8, wherein the volume of the extension layer is increased by epitaxially growing another crystal using a surface of the extension layer as a base after forming the gate sidewall;

and

the height of the insulating film is lowered after increasing the volume of the extension layer.