Stacked Circuits

• US 20090026524A1
• Filed: 07/27/2007
• Published: 01/29/2009
• Est. Priority Date: 07/27/2007
• Status: Abandoned Application

• Current Assignee: Qimonda AG (Infineon Technologies AG), Qimonda Flash GmbH (Infineon Technologies AG)
• Original Assignee: Qimonda Flash GmbH (Infineon Technologies AG)
• Inventors: Keitel-Schulz, Doris, Kreupl, Franz, Willer, Josef
• Application Number:
  US11/829,700
• Publication Number:
  US 20090026524A1
• Time in Patent Office: Days
• US Class Current: 257/316
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/83894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An integrated circuit includes a first integrated circuit layer including at least one first transistor channel region and having a wafer bonding interface. The integrated circuit may further include at least one second integrated circuit layer including at least one second transistor channel region and being arranged at the wafer bonding interface of the first integrated circuit layer.

Claims

1. An integrated circuit comprising:

a first integrated circuit layer comprising at least one first transistor channel region and having a wafer bonding interface; and

at least one second integrated circuit layer comprising at least one second transistor channel region and being arranged at the wafer bonding interface of the first integrated circuit layer.

2. The integrated circuit of claim 1, wherein the first integrated circuit layer comprises a first inter-layer dielectric forming at least part of the wafer bonding interface.

3. The integrated circuit of claim 1, wherein the second integrated circuit layer comprises:

a dielectric bonding layer arranged at the wafer bonding interface and having an operation layer support surface; and

an operation layer arranged at the operation layer support surface and comprising the at least one second transistor channel region.

4. The integrated circuit of claim 1, wherein the first and second transistor channel regions are substantially aligned to each other with respect to directions parallel to the wafer bonding interface.

5. The integrated circuit of claim 1, wherein the second integrated circuit layer comprises a p-doped well and an n-doped well, both extending substantially parallel to the wafer bonding interface and forming together a p-n-junction the direction substantially perpendicular to the wafer bonding interface.

6. The integrated circuit of claim 5, wherein the n-doped well and the p-doped well are electrically connected to voltage application contacts.

7. The integrated circuit of claim 1, wherein the second integrated circuit layer comprises a crystalline semiconductor layer having a plurality of isolation trenches formed therein.

8. The integrated circuit of claim 1, wherein at least one of the first and second integrated circuit layers comprise one or more non-volatile memory cells.

9. The integrated circuit of claim 8, wherein at least one of the first and second integrated circuit layers comprises one or more NAND flash memory circuits.

10. The integrated circuit of claim 1, comprising at least one SRAM cell that comprises a plurality of transistors, one of which comprises the first transistor channel region and one of which comprises the second transistor channel region.

11. A multi-layer NAND flash memory comprising:

a first integrated circuit layer comprising at least one first NAND flash cell string and having a wafer bonding interface; and

at least one second integrated circuit layer comprising at least one second NAND flash cell string and being wafer bonded to the wafer bonding interface of the first integrated circuit layer.

12. The multi-layer NAND flash memory of claim 11, wherein the first and the second NAND flash cell strings are aligned with respect to each other in directions parallel to the wafer bonding interface.

13. The multi-layer NAND flash memory of claim 11, further comprising a plurality of interlayer connections providing simultaneous electrical connection to the first and second NAND flash cell string.

14. A multi-media system comprising at least one multi-layer storage region having a plurality of storage sites arranged in two or more at least partly crystalline semiconductor storage layers separated by a wafer bonding interface, wherein at least some of the storage sites of different storage layers are electrically connected to each other via electrical interconnections penetrating the wafer bonding interface.

15. The multi-media system of claim 14, wherein the at least one multi-layer storage region comprises:

a first integrated circuit layer comprising at least one first transistor channel region and having a wafer bonding interface; and

at least one second integrated circuit layer comprising at least one second transistor channel region and being arranged at the wafer bonding interface of the first integrated circuit layer.

16. A method of fabricating an integrated circuit, the method comprising:

providing a first integrated circuit layer with a wafer bonding interface;

preparing a crystalline semiconductor layer; and

bonding the prepared crystalline semiconductor layer to the wafer bonding interface.

17. The method of claim 16, wherein providing the first integrated circuit layer comprises:

covering a processed semiconductor substrate with an inter-layer dielectric; and

planarizing a surface of the inter-layer dielectric to provide the wafer bonding interface as a substantially planar surface.

18. The method of claim 17, wherein planarizing the inter-layer dielectric comprises:

chemical-mechanical polishing the inter-layer dielectric down to an etch stop layer provided in the integrated circuit layer;

removing the etch stop layer;

chemical-mechanical polishing the inter-layer dielectric down to a hardmask layer provided in the integrated circuit layer; and

depositing a uniform oxide layer.

19. The method of claim 16, wherein preparing the crystalline semiconductor layer comprises providing the crystalline semiconductor layer with a substantially planar surface.

20. The method of claim 16, wherein preparing the crystalline semiconductor layer comprises arranging a dielectric bonding layer at the crystalline semiconductor layer and wherein the prepared crystalline semiconductor layer is bonded to the first integrated circuit layer by bonding the dielectric bonding layer to the wafer bonding interface.

21. The method of claim 16, wherein preparing the crystalline semiconductor layer comprises implanting an embrittlement zone in the crystalline semiconductor layer and wherein the method further comprises detaching part of the crystalline semiconductor layer at the embrittlement zone after bonding the prepared crystalline semiconductor layer to the wafer bonding interface.

22. The method of claim 16, wherein preparing the crystalline semiconductor layer comprises:

implanting at least one species of dopant into the crystalline semiconductor layer; and

annealing the crystalline semiconductor layer to form at least a first buried doped well.

23. The method of claim 16, further comprising applying a CMOS process to the bonded crystalline semiconductor layer.

24. The method of claim 23, wherein applying a CMOS process comprises structuring the crystalline semiconductor layer to form separated active areas electrically isolated from each other by dielectric filling material.

25. The method of claim 23, wherein applying a CMOS process comprises structuring the crystalline semiconductor layer to from active areas with a common extended doped well.

26. The method of claim 23, comprising substantially the same CMOS process flow for fabrication transistor structures in the first integrated circuit layer and in the bonded crystalline semiconductor layer.