VERTICAL FLOATING BODY CELL OF A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

• US 20090026541A1
• Filed: 10/03/2007
• Published: 01/29/2009
• Est. Priority Date: 07/27/2007
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: CHUNG, Sung Woong
• Granted Patent: US 7,663,188 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A semiconductor device includes a tube-type channel formed over a semiconductor substrate. The tube-type channel is connected to first and second conductive lines. A bias electrode is formed in the tube-type channel. The bias electrode is connected to the semiconductor substrate. An insulating film is disposed between the tube-type channel and the bias electrode. A surrounding gate electrode is formed over the tube-type channel.

Claims

1. A semiconductor device having a floating body cell structure, the device comprising:

a tube-type channel formed over a semiconductor substrate and connected to first and second conductive lines;

a bias electrode formed in the tube-type channel and connected to the semiconductor substrate;

an insulating film located between the tube-type channel and the bias electrode; and

a surrounding gate electrode formed over the tube-type channel.

2. The semiconductor device according to claim 1, wherein the first conductive line is connected to a bottom of the tube-type channel.

3. The semiconductor device according to claim 1, wherein the second conductive line is connected to a top of the tube-type channel.

4. The semiconductor device according to claim 1, wherein a top surface of the tube-type channel is circular or polygonal.

5. A method for fabricating a semiconductor device, the method comprising:

forming a conductive pillar over a semiconductor substrate;

etching a portion of the conductive pillar and the semiconductor substrate to form a conductive tube;

forming an insulating film over an inner sidewall of the conductive tube;

forming a bias electrode connected to the semiconductor substrate to fill the conductive tube;

forming a gate insulating film over an outer surface of the conductive tube; and

forming a surrounding gate electrode over the gate insulating film.

6. The method according to claim 5, wherein the forming-a-conductive-pillar step includes:

forming a conductive layer over the semiconductor substrate;

forming a hard mask layer over the conductive layer;

selectively etching the hard mask layer with an active region mask to form a hard mask pattern;

forming a spacer over a sidewall of the hard mask pattern; and

selectively etching the conductive layer using the hard mask pattern and the spacer as an etching mask to form the conductive pillar.

7. The method according to claim 6, wherein the conductive layer is formed of a p-type or undoped silicon layer to have a thickness in a range of about 500 Å

to 5,000 Å

.

8. The method according to claim 6, wherein the conductive layer is implanted with boron (B).

9. The method according to claim 6, wherein the hard mask layer is selected from the group consisting of an oxide film, a silicon nitride film and a combination thereof to have a thickness in a range of about 500 Å

to 5,000 Å

.

10. The method according to claim 6, wherein the spacer is formed of a silicon nitride film to have a thickness in a range of about 100 Å

to 500 Å

.

11. The method according to claim 6, wherein a shape of the active region mask is circular or polygonal.

12. The method according to claim 6, wherein the insulating film is formed of a silicon oxide film to have a thickness in a range of about 1 nm to 100 nm.

13. The method according to claim 5, wherein the bias electrode is selected from the group consisting of a single crystal silicon layer, a polysilicon layer, a titanium nitride (TiN) film, a tantalum nitride (TaN) film, a tungsten (W) layer and combinations thereof.

14. The method according to claim 5, wherein the gate insulating film is selected from the group consisting of a silicon oxide film, a hafnium oxide film, an aluminum oxide film, a zirconium oxide film, a hafnium silicon oxynitride film, a silicon nitride film and combinations thereof to have a thickness in a range of about 1 nm to 100 nm.

15. The method according to claim 5, wherein the gate electrode is selected from the group consisting of a polysilicon layer, a titanium (Ti) layer, a titanium nitride (TiN) film, a tantalum nitride (TaN) film, a tungsten (W) layer, an aluminum (Al) layer, a copper (Cu) layer, a tungsten silicide (WSi_x) layer and combinations thereof.

16. The method according to claim 5, further comprising forming a second conductive line connected to a top of the conductive tube.

17. The method according to claim 5, further comprising forming a first conductive line between the semiconductor substrate and the conductive tube.

18. The method according to claim 17, wherein the first conductive line is formed of a single crystal silicon layer by a silicon growth method to have a thickness in a range of about 100 Å

to 5,000 Å

.

19. The method according to claim 17, wherein the first conductive line is implanted with PH₃.

20. A method for fabricating a semiconductor device, the method comprising:

forming a conductive layer over the semiconductor substrate;

forming a hard mask layer over the conductive layer;

selectively etching the hard mask layer to form a hard mask pattern;

forming a spacer over a sidewall of the hard mask pattern;

selectively etching the conductive layer using the hard mask pattern and the spacer as an etching mask to form a conductive pillar;

etching a portion of the conductive pillar and the semiconductor substrate to form a conductive tube, wherein a first conductive line is formed between the semiconductor substrate and the conductive tube;

forming an insulating film over an inner sidewall of the conductive tube;

forming a bias electrode connected to the semiconductor substrate to fill the conductive tube;

forming a gate insulating film over an outer sidewall of the conductive tube; and

forming a surrounding gate electrode over the gate insulating film.

21. The method according to claim 20, further comprising forming a second conductive line connected to a top of the conductive tube.