Memory module capable of lessening shock stress

• US 20090026599A1
• Filed: 07/27/2007
• Published: 01/29/2009
• Est. Priority Date: 07/27/2007
• Status: Abandoned Application

• Current Assignee: Powertech Technology Inc
• Original Assignee: Powertech Technology Inc
• Inventors: Fan, Wen-Jeng
• Application Number:
  US11/878,891
• Publication Number:
  US 20090026599A1
• Time in Patent Office: Days
• US Class Current: 257/685
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0271 Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09145 Edge details
• CPC Class Codes: H05K 2201/10159 Memory
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 2201/2009 Reinforced areas, e.g. for a specific part of a flexible printed circuit
• CPC Class Codes: H05K 2203/1572 Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides

Abstract

A memory module capable of lessening shock stresses, primarily comprises a multi-layer printed circuit board (PCB), a plurality of memory packages, and a stress-buffering layer. The memory packages are disposed at least on one of the rectangular surfaces of the PCB. The stress-buffering layer is disposed at least on both short sides of the PCB and extended to the two rectangular surfaces to reduce the impact stresses. Preferably, the stress-buffering layer is further disposed on the other long side of the PCB opposite to the one with disposed gold fingers.

Claims

1. A memory module comprising:

a multi-layer printed circuit board (PCB) having a rectangular first surface, a rectangular second surface, a first long side, a second long side, and two short sides, the PCB including a plurality of gold fingers disposed on both surfaces of the first long side and a locking slot disposed on each short side;

a plurality of memory packages disposed at least on the first surface of the PCB; and

a stress-buffering layer disposed on both short sides of the PCB and extended to the first surface and the second surface.

2. The memory module of claim 1, wherein the memory packages are BGA packages with a plurality of solder balls.

3. The memory module of claim 2, wherein the PCB further includes a plurality of ball pads disposed on the first surface for disposing the solder balls.

4. The memory module of claim 3, wherein the ball pads are Non-Solder Mask Defined (NSMD) pads.

5. The memory module of claim 1, wherein the stress-buffering layer is moisture-proof.

6. The memory module of claim 1, wherein the stress-buffering layer is further disposed on the second long side.

7. The memory module of claim 1, wherein the stress-buffering layer is discontinuously disposed.

8. The memory module of claim 1, wherein the stress-buffering layer is not disposed in the locking slots.

9. The memory module of claim 1, wherein the stress-buffering layer is not disposed on the first long side.

10. The memory module of claim 1, wherein some of the memory packages are disposed on the second surface of the PCB.

11. The memory module of claim 1, wherein the stress-buffering layer has a U-shaped cross-section.