MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS

• US 20090026600A1
• Filed: 09/28/2007
• Published: 01/29/2009
• Est. Priority Date: 07/24/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeung, Boon Suan, Poo, Chia Yong, Koon, Eng Meow
• Granted Patent: US 7,843,050 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16258 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/17106 the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1064 Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49555 the bent parts being the outer leads
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49861 Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.

Claims

1. A stacked system of microelectronic die packages, comprising:

a first die package having a bottom side and including a first microelectronic die, a first dielectric casing at least partially covering the first die, and individual first metal leads coupled to the first die and having a first exterior surface;

a second die package having a top side attached to the bottom side of the first package and including a second microelectronic die, a second dielectric casing at least partially covering the second die and having a second lateral side, and individual second metal leads coupled to the second die and having a second exterior surface and an interior surface region that generally faces the lateral side, wherein the individual second leads are at least generally aligned with the individual first leads and project, at least in part, towards the first package; and

external inter-package connectors coupling a first portion of individual first exterior surfaces with a second portion of individual second exterior surfaces.

2. The stacked system of claim 1 wherein the individual second leads have an L-shape and physically contact corresponding individual first leads.

3. The stacked system of claim 1 wherein the individual second leads have a C-shape and include a tiered portion that projects towards the lateral side of the second casing.

4. The stacked system of claim 1 wherein the individual second leads are coupled to a bottom side of the second casing.

5. The stacked system of claim 1 wherein a bottom side of the second die package further includes package bonds that are coupled to metal bump pads associated with an interposer substrate.

6. The stacked system of claim 1 wherein the connectors project laterally outward from the first portion of the first exterior surfaces and the second portion of the second exterior surfaces.

7. The stacked system of claim 6 wherein the connectors further extend in between the first and second die packages, towards the lateral side of the second casing.

8. The stacked system of claim 1 wherein the lateral side of the second casing has a sloped profile and the interior surface regions of the leads are spaced apart from the lateral side by a gap.

9. The stacked system of claim 1 wherein the individual second leads of the second die package are separated from corresponding individual first leads of the first die package by vertical gaps, and wherein individual connectors comprise solder links that bridge the vertical gaps between corresponding pairs of first and second leads.

10. The stacked system of claim 1 wherein the first die has a first lateral dimension and the second die has a second lateral dimension different than the first lateral dimension, and wherein the first and second casings have equal lateral dimensions.

11. A computing system, comprising at least one of a processor, a memory, and an input/output device, wherein the computing system includes the stacked system according to claim 1.

12. A stacked system of microelectronic die packages, comprising:

a first microelectronic die package including a first dielectric casing having a first bottom side and first metal leads attached to the first bottom side;

a second microelectronic die package attached to the first die package and including a second dielectric casing having a lateral side, a second bottom side, and second metal leads coupled to the second bottom side, wherein individual second leads include a lateral portion that projects away from the lateral side, a bend, and an angled portion that projects from the bend towards a corresponding individual first lead; and

metal solder connectors attached to the individual first leads and a surface of individual angled portions of the second leads.

13. The stacked system of claim 12 wherein the angled portion is substantially sloped inward towards the lateral side of the second casing, and wherein the second leads directly contact corresponding first leads.

14. The stacked system of claim 12 wherein individual metal solder connectors attach individual angled portions to a surface of a corresponding first lead.

15. A stacked system of microelectronic devices, comprising:

a first microelectronic device having a first bottom side and first metal leads coupled to the first bottom side;

a second microelectronic device having a lateral side, a second bottom side, and second metal leads coupled to the second bottom side, the second leads including a lateral portion that laterally projects away from the lateral side, a tiered portion that laterally projects towards the lateral side, and an angled portion between the lateral portion and the tiered portion that positions the tiered portion above the lateral portion; and

metal solder bumps between individual first leads and individual tiered portions of the second leads.

16. The stacked system of claim 15 wherein the metal solder bumps are further attached to the individual second leads of the second microelectronic device at a surface of the angled portion that generally faces away from the lateral side of the second casing.

17. The stacked system of claim 15 wherein the tiered portion is separated from a corresponding first lead by a vertical distance of up to 60 microns.

18. The stacked system of claim 15 wherein the angled portion is substantially perpendicular to the lateral portion.

19. A microelectronic die package, comprising:

a microelectronic die;

a dielectric casing at least partially encapsulating the die and having a bottom side; and

a plurality of individual metal contacts coupled to the die and the bottom side of the casing and including a lateral portion that projects away from the casing, a bend curved away from the bottom side, and an angled portion that extends from the bend away from the bottom side of the casing, the angled portion having a first surface that faces the casing surface and a second surface that generally faces away from the casing surface, and wherein the second surface is configured to receive an external inter-package connector.

20. The device of claim 19 wherein the connector comprises at least one of a metal solder line and a metal solder bump.

21. The device of claim 20 wherein individual contacts have an L-shape and at least one of the first and second surfaces is configured as a wetting surface to attach to the connector.

22. The device of claim 20 wherein individual contacts have a C-shape that includes a tiered portion that extends inward from the angled portion towards the casing surface, the tiered portion having a third surface that generally faces away from the lateral portion and is configured as a wetting surface to attach with the connector.

23. A method of manufacturing a microelectronic device, the method comprising:

stacking a first die package having a first dielectric casing including a first bottom side on top of a second die package having a second dielectric casing including a second bottom side and a lateral side;

aligning first metal leads coupled to the first bottom side of the first die package with second metal leads coupled to the second bottom side of the second die package; and

forming individual external inter-package connectors attached to a first portion of individual first leads and to a second portion of individual second leads that are spaced apart from the lateral side of the second casing and project towards the first package.

24. The method of claim 23, further comprising compressing the second metal leads so that the second leads bend towards the lateral side of the second casing.

25. The method of claim 23 wherein forming the connectors comprises wetting metal solder to the first portion of the individual first leads and to the second portion of the individual second leads.

26. The method of claim 25, further comprising wetting the metal solder to interior and exterior surface portions of the individual second leads.

27. The method of claim 23 wherein the individual second leads comprise an L-shape, and wherein the second portion includes an angled portion of the individual second leads.

28. The method of claim 23 wherein the individual second leads comprise a C-shape, and wherein the second portion further includes a tier that projects towards the lateral side of the second casing.

29. The method of claim 28 wherein forming the connectors comprises wetting metal solder bumps to the first portion of the individual first leads and to the second portion of the individual second leads.

30. The method of claim 23, further comprising coupling package bond pads of the second die package to metal bump pads associated with an interposer substrate.

31. A method of manufacturing a microelectronic die package, the method comprising:

forming a dielectric casing that at least partially encapsulates a microelectronic die and includes a bottom side and a lateral side; and

forming individual metal contacts that have a lateral portion and an angled portion, the lateral portion being coupled to the bottom side of the casing and projecting away from the lateral side of the casing, the angled portion being spaced apart from the lateral side of the casing and extending away from the lateral portion such that an interior surface of the angled portion faces the lateral side of the casing, and wherein the angled portion is configured to wet to an external inter-package metal solder connector.

32. The method of claim 31, further comprising forming a dielectric spacer layer at the bottom side of the dielectric casing, wherein the spacer layer includes metal traces that electrically couple the die to individual contacts.

33. The method of claim 31 wherein the metal traces are selectively routed for coupling a portion of the contacts to the die.

34. The method of claim 31 wherein forming the individual metal contacts further comprises forming a tiered portion that extends from the angled portion inward towards the lateral side of the casing, wherein the tiered portion is configured to wet to the connector.

35. The method of claim 31 wherein the angled portions of the metal contacts are juxtaposed to the lateral side of the casing.