Capacitor save energy verification

• US 20090027014A1
• Filed: 07/25/2007
• Published: 01/29/2009
• Est. Priority Date: 07/25/2007
• Status: Active Grant

• Current Assignee: AgigA Tech Incorporated (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Sartore, Ronald H.
• Granted Patent: US 8,154,259 B2
• Time in Patent Office: Days
• US Class Current: 320/167
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/141 Battery and back-up supplies

Abstract

A memory subsystem is configured to obtain power from an external system and from at least one power capacitors. The memory subsystem includes logic to verify the power delivery capability of the power capacitors.

Claims

1. A memory subsystem configured to obtain power from an external system and from at least one power capacitors, comprising:

logic to verify a power delivery capability of the at least one power capacitors.

2. The memory subsystem of claim 1, wherein the logic to verify a power delivery capability of the at least one power capacitors further comprises:

logic to time at least one of a charge and discharge rate of the at least one capacitors using a predetermined load and voltage.

3. The memory subsystem of claim 1, wherein the logic to verify a power delivery capability of the at least one power capacitors further comprises:

logic to measure an ending voltage of the at least one capacitors at an end of a data backup operation from the volatile to the nonvolatile memories, and to determine if there is a sufficient voltage margin to provide reliable data backup.

4. The memory subsystem of claim 1, wherein the logic to verify a power delivery capability of the at least one power capacitors further comprises:

logic to measure a natural oscillation frequency of the at least one capacitors when the at least one capacitors are coupled to a predetermined impedance.

5. The memory subsystem of claim 1, wherein the logic to verify a power delivery capability of the at least one power capacitors further comprises:

logic to apply one or more of an operating temperature, operating voltage, and component age to capacitor power verification.

6. The memory subsystem of claim 1, wherein the logic to verify a power delivery capability of the at least one power capacitors further comprises:

logic to apply prior operational behavior of the at least one capacitors to capacitor power verification.

7. The memory subsystem of claim 1, wherein the logic to verify a power delivery capability of the at least one power capacitors further comprises:

logic to verify, upon restoration of external system power, that the at least one power capacitors have sufficient power to enable the data backup.

8. The memory subsystem of claim 1, wherein the logic to verify a power delivery capability of the at least one power capacitors further comprises:

logic to verify, after a time interval has passed, that the at least one power capacitors have sufficient power to enable the data backup.

9. The memory subsystem of claim 1, wherein the logic to verify a power delivery capability of the at least one power capacitors further comprises:

logic to verify, in response to a signal from the external system, that the at least one power capacitors have sufficient power to enable the data backup.

10. The memory subsystem of claim 1, further comprising:

logic to signal the external system of a result of power verification of the at least one capacitors.

11. The memory subsystem of claim 1, further comprising:

logic to signal the external system that the memory system is fully functional, non-functional, or functional in a degraded mode of operation, according to a result of power verification of the at least one capacitors.

12. The memory subsystem of claim 1, further comprising:

logic to place the memory subsystem in a degraded mode of operation if the power verification indicates that the at least one capacitors do not comprise enough power for a full data backup from volatile to nonvolatile memory.

13. The memory subsystem of claim 1, further comprising:

logic to prioritize the use of multiple capacitors for backup power according to results of power verification of the at least one capacitors.

14. A method of verifying the power delivery capability of at least one power capacitors in a memory subsystem, comprising:

verifying a power delivery capability of the at least one power capacitors.

15. The method of claim 14, wherein verifying a power delivery capability of the at least one power capacitors further comprises:

timing at least one of a charge and discharge rate of the at least one capacitors using a predetermined load and voltage.

16. The method of claim 14, wherein verifying a power delivery capability of the at least one power capacitors further comprises:

measuring an ending voltage of the at least one capacitors at an end of a data backup operation from the volatile to the nonvolatile memories, and determining if there is a sufficient voltage margin to provide reliable data backup.

17. The method of claim 14, wherein verifying a power delivery capability of the at least one power capacitors further comprises:

measuring a natural oscillation frequency of the at least one capacitors when the at least one capacitors are coupled to a predetermined impedance.

18. A device comprising:

a memory subsystem configured to obtain power from the device and from at least one power capacitors;

logic to cause power from the at least one power capacitor to be directed to memory components of the memory subsystem after device power to the memory subsystem is discontinued; and

logic to verify a power delivery capability of the at least one power capacitors.

19. The device of claim 18, further comprising:

logic to place the memory subsystem in a degraded mode of operation if the power verification indicates that the at least one capacitors do not comprise enough power for a data backup from volatile to nonvolatile memory.

20. The device of claim 18, further comprising:

logic to prioritize the use of multiple capacitors for backup power according to results of power verification of the at least one capacitors.