Pixel, organic light emitting display using the same, and associated methods

• US 20090027310A1
• Filed: 04/10/2008
• Published: 01/29/2009
• Est. Priority Date: 04/10/2007
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Yang-Wan
• Granted Patent: US 8,149,186 B2
• Time in Patent Office: Days
• US Class Current: 345/76
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0852 being a dynamic memory with more than one capacitor
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2320/045 Compensation of drifts in the characteristics of light emitting or modulating elements
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element

Abstract

A pixel including an organic light emitting diode, a second transistor controlling a current supplied to the organic light emitting diode, a pixel circuit configured to compensate a threshold voltage of the second transistor; and a compensating unit controlling a voltage of a gate electrode of the second transistor in order to compensate for deterioration of the organic light emitting diode. The compensating unit includes seventh and eighth transistors coupled in series between the organic light emitting diode and a first power source, the seventh and eight transistors being commonly connected to a fourth node therebetween, first and second feedback capacitors coupled in series between the fourth node and a second node, the second node being coupled to the gate electrode of the second transistor, and a ninth transistor coupled between a predetermined voltage source and a fifth node that is common to the first and second feedback capacitors.

Claims

1. A pixel, comprising:

an organic light emitting diode;

a second transistor controlling a current supplied to the organic light emitting diode;

a pixel circuit configured to compensate a threshold voltage of the second transistor; and

a compensating unit controlling a voltage of a gate electrode of the second transistor in order to compensate for deterioration of the organic light emitting diode, wherein the compensating unit includes;

seventh and eighth transistors coupled in series between the organic light emitting diode and a first power source, the seventh and eight transistors being commonly connected to a fourth node therebetween,

first and second feedback capacitors coupled in series between the fourth node and a second node, the second node being coupled to the gate electrode of the second transistor, and

a ninth transistor coupled between a predetermined voltage source and a fifth node that is common to the first and second feedback capacitors.

2. The pixel as claimed in claim 1, wherein the pixel circuit includes:

a first transistor having a gate electrode coupled to an i^th scan line, the first transistor being turned-on to couple a data line to a first electrode of the second transistor when a scan signal is supplied to the i^th scan line,

a third transistor having a gate electrode coupled to the i^th scan line, the third transistor being turned-on to couple a second electrode of the second transistor to the second node when the scan signal is supplied to the i^th scan line,

a sixth transistor having a gate electrode coupled to an i−

1^th scan line, the sixth transistor being turned-on to couple an initialization power source to the second node when a scan signal is supplied to the i−

1^th scan line,

a fourth transistor having a gate electrode coupled to an i^th light emitting control line, the fourth transistor being turned-on to couple the first electrode of the second transistor to the first power source when a light emitting control signal is not supplied to the i^th light emitting control line,

a fifth transistor having a gate electrode coupled to the i^th light emitting control line, the fifth transistor being turned-on to couple the second electrode of the second transistor to the organic light emitting diode when the light emitting control signal is not supplied to the i^th light emitting control line, and

a storage capacitor coupled between the second node and the first power source.

3. The pixel as claimed in claim 2, wherein the predetermined voltage source is the initialization power source.

4. The pixel as claimed in claim 1, wherein the seventh and eighth transistors operate in opposition to one another.

5. The pixel as claimed in claim 1, wherein the eighth and ninth transistors operate in opposition to one another.

6. The pixel as claimed in claim 5, wherein the eighth transistor is a PMOS transistor and the ninth transistor is an NMOS transistor.

7. The pixel as claimed in claim 1, wherein the predetermined voltage source is the first power source.

8. The pixel as claimed in claim 1, wherein:

the seventh and eighth transistors have gate electrodes coupled to an i+2^th light emission control line, and

the seventh transistor is an NMOS transistor and the eighth transistor is a PMOS transistor.

9. A display, comprising;

a scan driver coupled to scan lines and light emitting control lines;

a data driver coupled to data lines; and

a plurality of pixels coupled to the scan lines, the data lines, and the light emitting control lines, wherein each of the pixels includes;

an organic light emitting diode,

a second transistor controlling a current supplied to the organic light emitting diode,

a pixel circuit configured to compensate a threshold voltage of the second transistor, and

a compensating unit controlling a voltage of a gate electrode of the second transistor in order to compensate for deterioration of the organic light emitting diode, the compensating unit including;

seventh and eighth transistors coupled in series between the organic light emitting diode and a first power source, the seventh and eight transistors being commonly connected to a fourth node therebetween,

first and second feedback capacitors coupled in series between the fourth node and a second node, the second node being coupled to the gate electrode of the second transistor, and

a ninth transistor coupled between a predetermined voltage source and a fifth node that is common to the first and second feedback capacitors.

10. The display as claimed in claim 9, wherein the pixel circuit includes:

a first transistor having a gate electrode coupled to an i^th scan line, the first transistor being turned-on to couple a data line to a first electrode of the second transistor when a scan signal is supplied to the i^th scan line,

a third transistor having a gate electrode coupled to the i^th scan line, the third transistor being turned-on to couple a second electrode of the second transistor to the second node when the scan signal is supplied to the i^th scan line,

a sixth transistor having a gate electrode coupled to an i−

1^th scan line, the sixth transistor being turned-on to couple an initialization power source to the second node when a scan signal is supplied to the i−

1^th scan line,

a fourth transistor having a gate electrode coupled to an i^th light emitting control line, the fourth transistor being turned-on to couple the first electrode of the second transistor to the first power source when a light emitting control signal is not supplied to the i^th light emitting control line,

a fifth transistor having a gate electrode coupled to the i^th light emitting control line, the fifth transistor being turned-on to couple the second electrode of the second transistor to the organic light emitting diode when the light emitting control signal is not supplied to the i^th light emitting control line, and

a storage capacitor coupled between the second node and the first power source.

11. The display as claimed in claim 10, wherein the initialization power source is set to a voltage that is lower than a voltage of a data signal applied to the data line.

12. The display as claimed in claim 10, wherein:

the scan driver supplies a light emitting control signal to the i^th light emitting control line such that it overlaps with scan signals supplied to the i−

1^th scan line and the i^th scan line, and

the scan driver supplies a light emitting control signal to an i+1^th light emitting control line such that it overlaps with scan signals supplied to the i^th scan line and an i+1^th scan line.

13. The display as claimed in claim 12, wherein:

the seventh transistor is turned on when the scan signal is supplied to the i+1^th scan line, and

the eighth transistor is turned off when the light emitting control signal is supplied to the i+1^th light emitting control line.

14. The display as claimed in claim 13, wherein the eighth and ninth transistors operate in opposition to one another.

15. The display as claimed in claim 14, wherein the eighth transistor is a PMOS transistor and the ninth transistor is an NMOS transistor.

16. The display as claimed in claim 12, wherein:

the scan driver supplies a light emitting control signal to an i+2^th light emitting control line such that it overlaps with the scan signal supplied to the i+1^th scan line,

the seventh transistor is turned on when the light emitting control signal is supplied to the i+2^th light emitting control line, and

the eighth transistor is turned off when the light emitting control signal is supplied to the i+2^th light emitting control line.

17. The display as claimed in claim 16, wherein:

the seventh and eighth transistors have gate electrodes coupled to the i+2^th light emission control line,

the seventh transistor is an NMOS transistor, and

the eighth transistor is a PMOS transistor.

18. The display as claimed in claim 16, wherein the predetermined voltage source is the initialization power source.

19. The display as claimed in claim 10, wherein:

the initialization power source initializes a voltage of the gate electrode of the second transistor, and

the third transistor diode-connects the second transistor to charge a voltage corresponding to a threshold voltage of the second transistor and a data signal in the storage capacitor.

20. The display as claimed in claim 19, wherein:

the seventh transistor couples the fourth node to the organic light emitting diode while a current is supplied to the organic light emitting diode, such that a voltage at the organic light emitting diode is applied to the fourth node,

subsequently, the eight transistor couples the fourth node to the first power source, such that the voltage of the fourth node is raised to the voltage of the first power source, and

the first and second feedback capacitors transmit the voltage rise of the fourth node to the second node.

21. The display as claimed in claim 9, wherein the seventh and eighth transistors operate in opposition to one another.

22. A method of driving a display having seventh and eighth transistors coupled in series between an anode electrode of an organic light emitting diode and a first power source, and first feedback and second feedback capacitors coupled in series between a fourth node, which is a node common to the seventh and eighth transistors, and a gate electrode of a driving transistor, the method including:

initializing a voltage of the gate electrode of the driving transistor with a voltage of an initialization power source;

charging a voltage corresponding to a threshold voltage of the driving transistor and a data signal in a storage capacitor by diode-connecting the driving transistor;

supplying a current corresponding to the voltage charged in the storage capacitor to the organic light emitting diode;

applying a voltage applied to the organic light emitting diode to the fourth node;

maintaining a fifth node, which is common to the first and second feedback capacitors, at a constant voltage while charging the voltage in the storage capacitor and supplying the voltage applied to the organic light emitting diode to the fourth node; and

controlling the voltage of the gate electrode of the driving transistor by setting the fifth node to a floating stat and, at the same time, raising the voltage of the fourth node to the voltage of the first power source.

23. The method as claimed in claim 22, wherein the constant voltage is the voltage supplied from any one of the initialization power source and the first power source.

24. The method as claimed in claim 22, wherein the initialization power source is set to a voltage that is lower than that of the data signal.

25. The method as claimed in claim 22, wherein the seventh and eighth transistors operate in opposition to one another.