Method, apparatus, and system for reduction of line processing memory size used in image processing

• US 20090027727A1
• Filed: 07/25/2007
• Published: 01/29/2009
• Est. Priority Date: 07/25/2007
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Ovsiannikov, Ilia
• Granted Patent: US 8,462,377 B2
• Time in Patent Office: Days
• US Class Current: 358/1.170
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A method, apparatus, and system are provided by which image line data of an image frame is compressed before being stored to image line memory used in multiple image line processing.

Claims

1. A method of image processing, comprising:

compressing each of a plurality of successive lines of received image data;

storing the compressed successive lines of image data into respective line buffers; and

performing an image processing operation using the image data stored in the line buffers.

2. The method of claim 1, further comprising:

decompressing the image data stored in the line buffers before performing said image processing operation.

3. The method of claim 1, wherein the acts of compressing, storing, and performing an image processing operation are performed by circuitry on a single integrated circuit chip.

4. The method of claim 1, wherein said image processing operation includes defect correction processing.

5. The method of claim 1, wherein said image processing operation includes noise reduction processing.

6. The method of claim 1, wherein said image processing operation includes optical crosstalk reduction processing.

7. The method of claim 1, wherein said image processing operation includes demosaic processing.

8. The method of claim 1, wherein said image processing operation includes image resizing.

9. The method of claim 1, wherein said image processing operation includes image sharpening.

10. The method of claim 1, wherein the act of compressing comprises converting M-bit image pixel values to lesser N-bit image pixel values, where M and N are integers and N is based on a signal-to-noise ratio of the M-bit image pixel values.

11. The method of claim 10, wherein the act of compressing encodes the lines of image data based on a linear encoding function.

12. The method of claim 11, wherein the linear encoding function is a piecewise linear transform comprising two or more linear segments that map the M-bit and N-bit image pixel values to one another.

13. The method of claim 1, wherein the line buffers form a line memory of serially connected FIFO line buffers, and each of the line buffers directly reads out the respectively stored line of image data from the line memory.

14. The method of claim 13, further comprising decompressing the lines of image data read out from the line memory, wherein the image processing operation is performed on the decompressed lines of image data.

15. The method of claim 14, wherein the image processing operation is performed on the decompressed lines of image data and a line of image data being input to a sequentially first line buffer of the serially connected FIFO line buffers.

16. An imaging device, comprising:

an image sensing array for outputting successive lines of image data;

a compressor for respectively compressing lines of received image data;

a line memory for storing a number of lines of the compressed image data; and

a processor circuit for performing an image processing operation using the image data stored in the line memory.

17. The imaging device of claim. 16, wherein the line memory is configured to serially store successive lines of compressed image data in respective line memory storage locations in a FIFO arrangement.

18. The imager device of claim 17, further comprising:

a decompressor for decompressing the stored lines of compressed image data for use by the processor circuit.

19. The imager device of claim 18, wherein said image processor circuit simultaneously reads out the decompressed image data from the line memory.

20. The method of claim 19, wherein the image processor circuit performs the image processing operation on the decompressed lines of image data and a line of uncompressed image data being input to a sequentially first line memory storage location of the serially connected FIFO line memory storage locations.

21. The imager device of claim 16, wherein the image sensing array, compressor, line memory, and image processor circuit are each part of a single integrated circuit chip.

22. The imager device of claim 16, wherein said image processing operation includes defect correction processing.

23. The imager device of claim 16, wherein said image processing operation includes noise reduction processing.

24. The imager device of claim 16, wherein said image processing operation includes optical crosstalk reduction processing.

25. The imager device of claim 16, wherein said image processing operation includes demosaic processing.

26. The imager device of claim 16, wherein said image processing operation includes image resizing.

27. The imager device of claim 16, wherein said image processing operation includes image sharpening.

28. The imager device of claim 16, wherein the compressor converts M-bit image pixel values to lesser N-bit image pixel values, where M and N are integers and N is based on a signal-to-noise ratio of the M-bit image pixel values.

29. The imager device of claim 28, wherein the compressor encodes the lines of image data based on a linear encoding function.

30. The imager device of claim 29, wherein the linear encoding function is a piecewise linear transform comprising two or more linear segments that map the M-bit and N-bit image pixel values to one another.

31. The method of claim 17, wherein each of the line storage locations directly reads out the respectively stored line of image data from the line memory.