Frequency modulation device and switching mode power supply using the same

• US 20090028235A1
• Filed: 07/25/2008
• Published: 01/29/2009
• Est. Priority Date: 07/26/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Korea Semiconductor Limited (ON Semiconductor Corporation)
• Inventors: Koo, Gwan-Bon, Park, Young-Bae
• Granted Patent: US 8,194,425 B2
• Time in Patent Office: Days
• US Class Current: 375/238
• CPC Class Codes: H03K 7/06 Frequency or rate modulation, i.e. PFM or PRM

Abstract

The present invention relates to a frequency modulation device and a switching mode power supply using the frequency modulation device. To prevent electromagnetic interference (EMI), it is required to slightly vary a switching operation frequency in an SMPS operation. In some embodiments, at least one first signal having a predetermined cycle is generated, a second signal corresponding to a level of a first signal is generated at a turn-off time of a switch, a first reference voltage having at least two different levels is generated according to the second signal, and an oscillator signal for increasing along a first slope during a first period and decreasing along a second slope during a second period between the first reference voltage and a second reference voltage having a level that is different from the first reference voltage is generated.

Claims

1. A frequency modulation device comprising:

a counter for using a first clock signal having a predetermined cycle and generating at least one first signal having a cycle of an integer times the cycle of the first clock signal;

a latch unit for detecting the first signal at a predetermined time and generating a second signal corresponding to a level of the first signal;

a reference signal generator for generating a first reference signal having at least two different levels according to the second signal; and

a pulse width modulation (PWM) oscillator for generating an oscillator signal that increases with a first slope and decreases with a second slope between the first reference signal and a second reference signal, wherein the second reference signal has a level that is different from that of the first reference signal.

2. The frequency modulation device of claim 1, wherein the PWM oscillator comprises:

a capacitor;

a first comparator for comparing the first reference signal and the oscillator signal;

a second comparator for comparing the second reference signal and the oscillator signal;

a current source for charging the capacitor;

a sync-current source for discharging the capacitor;

a first switch coupled between the capacitor and the current source;

a second switch coupled between the capacitor and the sync-current source; and

an SR flipflop for controlling an on/off operation of the first and second switches according to output signals of the first and second comparators,

wherein the oscillator signal has a voltage that corresponds to a voltage charged in the capacitor, the second switch is turned off when the first switch is turned on, and the second switch is turned on when the first switch is turned off.

3. The frequency modulation device of claim 2, wherein the first slope is determined according to a capacitance of the capacitor and the current source, and the second slope is determined according to the capacitance of the capacitor and the sync-current source.

4. The frequency modulation device of claim 2, wherein a set terminal of the SR flipflop is coupled to an output terminal of the first comparator, a reset terminal of the SR flipflop is coupled to an output terminal of the second comparator, the first reference signal is higher than the second reference signal, the first switch is turned off when the oscillator signal is higher than the first reference signal, and the second switch is turned off when the oscillator signal is reduced to the second reference signal.

5. The frequency modulation device of claim 4, wherein the oscillator signal and the first reference signal are respectively input to an inverted terminal and a non-inverted terminal of the first comparator, the second reference signal and the oscillator signal are respectively input to an inverted terminal and a non-inverted terminal of the second comparator, the first and second switches are respectively driven in response to an output signal of an inverted output terminal of the SR flipflop and an output signal of an output terminal of the SR flipflop and are turned on in response to a signal of a high level, and the SR flipflop is configured to output the signal of the high level to the output terminal and a signal of a low level to the inverted output terminal when the set terminal of the SR flipflop receives the signal of the low level and the reset terminal of the SR flipflop receives the signal of the high level, and to output the signal of the low level to the output terminal and the signal of the high level to the inverted output terminal when the set terminal receives the signal of the high level and the reset terminal receives the signal of the low level.

6. The frequency modulation device of claim 2, wherein a reset terminal of the SR flipflop is coupled to an output terminal of the first comparator, a set terminal of the SR flipflop is coupled to an output terminal of the second comparator, the second reference signal is higher than the first reference signal, the first switch is turned off when the oscillator signal is higher than the second reference signal, and the second switch is turned off when the oscillator signal is reduced to the first reference signal.

7. The frequency modulation device of claim 1, wherein

the counter includes a first toggle flipflop for generating the first signal by using the first clock signal,

the first toggle flipflop is configured to receive a signal of a first level at a first first toggle flipflop input terminal and the first clock signal at a second first toggle flipflop input terminal,

the counter being synchronized with a first time of the first clock signal to generate the first signal in response to the signal of the first level,

the latch unit including a first D flipflop including a first first D flipflop input terminal receiving the first signal and a second first D flipflop input terminal receiving an external control signal,

the predetermined time is a time where a level of the control signal is varied from a first level to a second level, and

the reference signal generator includes at least three resistors coupled in series, a first switch is coupled in parallel to one of three resistors, and the first switch is turned on/off according to the second signal.

8. The frequency modulation device of claim 7, wherein

the counter includes a second toggle flipflop including a first second toggle flipflop input terminal receiving the signal of the first level and a second second toggle flipflop input terminal receiving the first signal and is synchronized with a second time of the first signal to generate a third signal in response to the signal of the first level,

the latch unit further includes a second D flipflop including a first second D flipflop input terminal receiving the third signal and a second second D flipflop input terminal signal receiving the control signal,

the second D flipflop is configured to detect the third signal at the predetermined time to generate a fourth signal corresponding to a level of the third signal,

the reference signal generator further includes a second resistor coupled in series to the at least three resistors and further includes a second switching element coupled in parallel to the second resistor, and

the second switching element is turned on/off according to the fourth signal.

9. The frequency modulation device of claim 8, wherein the first time is a rising edge timing of the first clock signal, a second time is a rising edge timing of the first signal, the first toggle flipflop is configured to invert a current output state of the first signal in response to the signal of the first level at the first time, and the second toggle flipflop is configured to invert a current output state of the third signal in response to the signal of the first level at the second time.

10. The frequency modulation device of claim 1, wherein the counter includes a first toggle flipflop for generating the first signal by using the first clock signal, a signal of a first level is input to a first first toggle flipflop input terminal, the first clock signal is input to a second first toggle flipflop input terminal, the counter is synchronized with a first time of the first clock signal to generate the first signal in response to the signal of the first level,

the latch unit includes a first D flipflop including a first first D flipflop input terminal configured to receive the first signal and a second first D flipflop input terminal configured to receive an external control signal,

the predetermined time is a time where a level of the control signal is varied from the first level to a second level, and

the reference signal generator includes a current copy circuit for copying a reference current in a predetermined ratio and a switching element electrically coupled to the current copy circuit.

11. A switching mode power supply (SMPS) comprising a transformer and a main switch coupled to a primary coil of the transformer, for supplying power to a secondary coil of the transformer according to a switching operation of the main switch, the SMPS comprising:

a frequency modulation device for generating an oscillator signal having a first cycle; and

a switch controller for generating a gate control signal for controlling the main switch by using a pulse width modulation (PWM) clock signal having a second cycle corresponding to the first cycle, a feedback signal corresponding to a voltage of the secondary coil of the transformer, and a detection signal corresponding to a current flowing through the main switch,

wherein the frequency modulation device is configured to generate at least one first signal having a predetermined cycle, a second signal corresponding to a level of the first signal at a reference time when a level of the gate control signal is changed, a first reference signal having at least two different levels according to the second signal, and an oscillator signal that increases along a first slope during a first period and decreases along a second slope during a second period between the first reference signal and a second reference signal having a level that is different from that of the first reference signal, and the first cycle corresponds to a sum of the first and second periods.

12. The SMPS of claim 11, wherein the frequency modulation device comprises:

a counter for using a first clock signal having a predetermined cycle to generate at least one first signal having a cycle of an integer times the cycle of the first clock signal;

a latch unit for detecting the first signal at the reference time, and generating the second signal corresponding to the level of the first signal;

a reference signal generator for generating the first reference signal having at least two different levels according to the second signal; and

a PWM oscillator for generating the oscillator signal.

13. The SMPS of claim 12, wherein the PWM oscillator comprises:

a capacitor;

a first comparator for comparing the first reference signal and the oscillator signal;

a second comparator for comparing the second reference signal and the oscillator signal;

a current source for charging the capacitor;

a sync-current source for discharging the capacitor;

a first switch coupled between the capacitor and the current source;

a second switch coupled between the capacitor and the sync-current source; and

an SR flipflop for controlling an on/off operation of the first and second switches according to output signals of the first and second comparators,

wherein the oscillator signal has a voltage that is the same as that charged in the capacitor, the second switch is turned of when the first switch is turned on, and the second switch is turned on when the first switch is turned off.

14. The SMPS of claim 13, wherein the first slope is determined according to capacitance of the capacitor and the source-current source, and the second slope is determined according to the capacitance of the capacitor and the sync-current source.

15. The SMPS of claim 13, wherein a set terminal of the SR flipflop is coupled to an output terminal of the first comparator, a reset terminal of the SR flipflop is coupled to an output terminal of the second comparator, the first reference signal is higher than the second reference signal, the first switch is turned off when the oscillator signal is higher than the first reference signal, and the second switch is turned off when the oscillator signal is reduced to the second reference signal.

16. The SMPS of claim 15, wherein the oscillator signal and the first reference signal are respectively input to an inverted terminal and a non-inverted terminal of the first comparator, the second reference signal and the oscillator signal are respectively input to an inverted terminal and a non-inverted terminal of the second comparator, the first and second switches are respectively driven in response to an output signal of an inverted output terminal of the SR flipflop and an output signal of an output terminal of the SR flipflop and are turned on in response to a signal of a high level, and the SR flipflop outputs the signal of the high level to the output terminal and a signal of a low level to the inverted output terminal when the set terminal of the SR flipflop receives the signal of the low level and the reset terminal of the SR flipflop receives the signal of the high level, and outputs the signal of the low level to the output terminal and the signal of the high level to the inverted output terminal when the set terminal receives the signal of the high level and the reset terminal receives the signal of the low level.

17. The SMPS of claim 12, wherein

the counter includes a first toggle flipflop for generating the first signal by using the first clock signal,

a signal of a first level is input to a first input terminal of the first toggle flipflop,

the first clock signal is input to a second input terminal of the first toggle flipflop,

the counter is synchronized with a first time of the first clock signal to generate the first signal in response to the signal of the first level,

the latch unit includes a first D flipflop including a first input terminal receiving the first signal and a second input terminal externally receiving a control signal,

the predetermined time is a time where a level of the control signal is varied from a first level to a second level, and

the reference signal generator includes at least three resistors coupled in series, a first switch is coupled in parallel to one of three resistors, and the first switch is turned on/off according to the second signal.

18. The SMPS of claim 17, wherein

the counter further includes a second toggle flipflop including a first input terminal receiving the signal of the first level and a second input terminal receiving the first signal and is synchronized with a second point of time of the first signal to generate a third signal in response to the signal of the first level,

the latch unit further includes a second D flipflop including a first input terminal receiving the third signal and a second input signal receiving the control signal,

the second D flipflop configured to detect the third signal at the predetermined point of time to generate a fourth signal corresponding to a level of the third signal,

the reference signal generator further includes a second resistor coupled in series to the at least three resistors and further includes a second switching element coupled in parallel to the second resistor, and

the second switching element is turned on/off according to the fourth signal.

19. The SMPS of claim 18, wherein the first time is rising edge timing of the first clock signal, a second point of time is rising edge timing of the first signal, the first toggle flipflop inverts a current output state of the first signal in response to the signal of the first level at the first point of time, and the second toggle flipflop inverts a current output state of the third signal in response to the signal of the first level at the second point of time.

20. The SMPS of claim 12, wherein the counter includes a first toggle flipflop for generating the first signal by using the first clock signal, a signal of a first level is input to a first input terminal of the first toggle flipflop, the first clock signal is input to a second input terminal of the first toggle flipflop, the counter is synchronized with a first point of time of the first clock signal to generate the first signal in response to the signal of the first level,

the latch unit includes a first D flipflop including a first input terminal receiving the first signal and a second input terminal externally receiving a control signal,

the predetermined time is a point of time where a level of the control signal is varied from the first level to a second level, and

the reference signal generator includes a current copy circuit for copying a reference current in a predetermined ratio and a switching element electrically coupled to the current copy circuit.

21. The SMPS of claim 11, wherein the switch controller further includes a PWM oscillator for detecting a maximum value or a minimum value of the oscillator signal, determining the first cycle, and generating the PWM clock signal having the second cycle that is the same as the first cycle;

the switch controller configured to generate the gate control signal for turning off the main switch when the detection signal reaches a level of the feedback signal, and to generate the gate control signal for turning on the main switch at a first time where a level of the PWM clock signal is varied from a first level to a second level after the main switch is turned off.

22. The SMPS of claim 21, wherein the switch controller comprises:

a comparator for comparing the detection signal and the feedback signal;

an SR flipflop for receiving an output signal of the comparator and the PWM clock signal, outputting a signal of a fourth level to a first output terminal when the output signal of the comparator is a third level, and generating a signal of a fifth level according to the PWM clock signal at the first point of time; and

a logic operation unit for receiving an output signal of the SR flipflop and the PWM clock signal and performing a logic operation of the input signal, and the switch controller for generating the gate control signal for turning on the main switch according to a signal output by the logic operation unit when the two input signals are sixth levels.

23. The SMPS of claim 22, wherein the frequency modulation device comprises:

a counter for using a first clock signal having a predetermined cycle to generate at least one first signal having a cycle of an integer times the cycle of the first clock signal;

a latch unit for detecting the reference time using the output signal of the comparator, detecting the first signal at the reference time, and generating the second signal corresponding to the level of the first signal;

a reference signal generator for generating the first reference signal having at least two different levels according to the second signal; and

a PWM oscillator for generating the oscillator signal.

24. The SMPS of claim 22, wherein the first, third, and fourth levels are high levels, and the second, fifth, and sixth levels are low levels.

25. The SMPS of claim 11, further comprising an integrated circuit in which the main switch and the switch controller are integrated in one packaging.

26. The SMPS of claim 11, further comprising an integrated circuit in which the main switch and the switch controller are respectively formed in different packagings.