Multi-level Cell Flash Memory and Method of Programming the Same

• US 20090031074A1
• Filed: 07/22/2008
• Published: 01/29/2009
• Est. Priority Date: 07/27/2007
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Son, Chang-Il
• Application Number:
  US12/177,491
• Publication Number:
  US 20090031074A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits

Abstract

Provided is a flash memory having a multi-level cell (MLC) and a method of programming the same. The method includes identifying a set of first patterns from input data, determining whether there is a set of second patterns stored within the flash memory that is of a number substantially similar to the number of the first patterns, and programming the input data as a most significant bit (MSB) in a location of the flash memory where the identified set of second patterns is stored when it is determined that there is a set of second patterns stored within the flash memory that is of a number substantially similar to the number of first patterns.

Claims

1. A method of programming a flash memory, the method comprising:

identifying a set of first patterns from input data;

determining whether there is a set of second patterns stored within the flash memory that is of a number substantially similar to the number of the first patterns; and

programming the input data as a most significant bit (MSB) in a location of the flash memory where the identified set of second patterns is stored when it is determined that there is a set of second patterns stored within the flash memory that is of a number substantially similar to the number of first patterns.

2. The method of claim 1, wherein the input data is programmed as a LSB in the flash memory when it is determined that there is not a set of second patterns stored within the flash memory that is of a number substantially similar to the number of first patterns.

3. The method of claim 2, wherein the flash memory is blank.

4. The method of claim 1, wherein, when data stored in an LSB programmed cell of the flash memory and the input data have the same value, only a flag cell of the LSB programmed cell is programmed in writing the input data to the flash memory cell.

5. The method of claim 1, wherein the set of first patterns are identified based on a file format of the input data or based on whether the input data are compressed.

6. The method of claim 1, wherein the flash memory is a multi-level cell (MLC).

7. A memory device comprising:

a processor identifying a set of first patterns from within input data received by a host; and

a memory storing a set of second patterns,

wherein the processor counts the numbers of identified first patterns and outputs the counted number of first patterns;

determines whether there is a set of second patterns stored within the memory that is of a number substantially similar to the numbers of the first patterns; and

programs the input data as an MSB in a location of the memory where the identified set of second patterns is stored when it is determined that there is a set of second patterns stored within the memory that is of a number substantially similar to the number of first patterns.

8. The memory device of claim 7, wherein the input data is programmed as a LSB in the memory when it is determined that there is not a set of second patterns stored within the memory that is of a number substantially similar to the number of first patterns.

9. The memory device of claim 7, wherein the memory is blank.

10. The memory device of claim 7, wherein, when data stored in an LSB programmed cell of the memory and the input data have the same value, only a flag cell of the LSB programmed cell is programmed in writing the input data to the memory cell.

11. The memory device of claim 7, wherein the set of first patterns are identified based on a file format of the input data or based on whether the input data are compressed.

12. The memory device of claim 7, wherein the memory comprises a random access memory (RAM) and a flash memory.

13. The memory device of claim 12, wherein, before a power source is turned off, the processor stores the set of first patterns and the second patterns, which are stored in the RAM, into the flash memory.

14. The memory device of claim 12, wherein, when a power source is turned on, the processor stores the set of first patterns and the second patterns, which are stored in the flash memory, into the RAM.

15. The memory device of claim 7, wherein the memory includes an MLC flash memory.

16. A method of programming a flash memory, the method comprising:

determining a pattern of input data;

searching within a memory for LSB pattern information that is substantially similar to the determined pattern of input data; and

programming the input data as an MSB in a location of the flash memory where the similar LSB pattern information is stored when the similar LSB pattern is found to be in the memory.

17. The method of claim 16, wherein the determining of the pattern comprises:

determining a plurality of LSB patterns; and

counting the respective numbers of the LSB patterns in the input data and outputting the numbers of first patterns.

18. The method of claim 17, wherein the LSB pattern information stored in the memory comprises the numbers of second patterns representing the respective numbers of the LSB patterns.

19. The method of claim 16, wherein the searching of the LSB pattern information comprises searching the most similar numbers of the second patterns among the numbers of the first patterns and the LSB pattern information stored in the memory.