Variable partitioning in a hybrid memory subsystem

• US 20090031098A1
• Filed: 07/25/2007
• Published: 01/29/2009
• Est. Priority Date: 07/25/2007
• Status: Active Grant

• Current Assignee: AgigA Tech Incorporated (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Sartore, Ronald H.
• Granted Patent: US 8,046,546 B2
• Time in Patent Office: Days
• US Class Current: 711/162
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1451 by selection of backup contents
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 5/144 Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby

Abstract

A memory subsystem may include logic to make available to the device into which it is installed at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure. The logic may make available to the device at least one portion of the volatile memory that will not be backed up to the nonvolatile memory in the event of device power failure, and make available to the device at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory.

Claims

1. A memory subsystem for use in a device, comprising:

volatile memory;

nonvolatile memory; and

logic to make available to the device at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure; and

logic to make available to the device at least one portion of the volatile memory that will not be backed up to the nonvolatile memory in the event of device power failure.

2. The memory subsystem of claim 1, further comprising:

logic to make available to the device at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory.

3. The memory subsystem of claim 1, further comprising:

one or more configuration registers to enable the device to specify the at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure.

4. The memory subsystem of claim 2, further comprising:

one or more configuration registers to enable the device to specify the at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory.

5. A device comprising:

a memory subsystem comprising volatile memory, nonvolatile memory, and

logic to make available to the device at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure; and

logic to make available to the device at least one portion of the volatile memory that will not be backed up to the nonvolatile memory in the event of device power failure.

6. The device of claim 5, the memory subsystem further comprising:

logic to make available to the device at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory.

7. The device of claim 5, the memory subsystem further comprising:

one or more configuration registers to enable the device to specify the at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure.

8. The device of claim 6, the memory subsystem further comprising:

one or more configuration registers to enable the device to specify the at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory.

9. A method of configuring memory in a device, comprising:

configuring at least one portion of volatile memory of a memory system of the device to be backed up to nonvolatile memory of the memory system in the event of device power failure; and

configuring at least one portion of the volatile memory to be not backed up to the nonvolatile memory in the event of device power failure.

10. The method of claim 9, further comprising:

configuring at least one portion of the nonvolatile memory to be not reserved for backups from the volatile memory.

11. A memory subsystem for use in a device, comprising:

volatile memory;

nonvolatile memory; and

logic to make available to the device at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure; and

logic to make available to the device at least one portion of the nonvolatile memory that will not be used to back up the volatile memory in the event of device power failure.

12. The memory subsystem of claim 11, further comprising:

logic to make available to the device at least one portion of the volatile memory that is not backed up to the nonvolatile memory.

13. The memory subsystem of claim 11, further comprising:

one or more configuration registers to enable the device to specify the at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure.

14. The memory subsystem of claim 12, further comprising:

one or more configuration registers to enable the device to specify the at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory.

15. A device comprising:

a memory subsystem comprising volatile memory, nonvolatile memory, and

logic to make available to the device at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure; and

logic to make available to the device at least one portion of the nonvolatile memory that will not be used to back up the volatile memory in the event of device power failure.

16. The device of claim 15, the memory subsystem further comprising:

logic to make available to the device at least one portion of the volatile memory that will not be backed up to the nonvolatile memory in the event of device power failure.

17. The device of claim 15, the memory subsystem further comprising:

one or more configuration registers to enable the device to specify the at least one portion of the volatile memory that will be backed up to the nonvolatile memory in the event of device power failure.

18. The device of claim 16, the memory subsystem further comprising:

one or more configuration registers to enable the device to specify the at least one portion of the nonvolatile memory that is not reserved for backups from the volatile memory.

19. A method of configuring memory in a device, comprising:

configuring at least one portion of volatile memory of a memory system of the device to be backed up to nonvolatile memory of the memory system in the event of device power failure; and

configuring at least one portion of the nonvolatile memory to not be used for backup of the volatile memory in the event of device power failure.

20. The method of claim 19, further comprising:

configuring at least one portion of the volatile memory to not be backed up to the nonvolatile memory.