Power interrupt recovery in a hybrid memory subsystem

• US 20090031099A1
• Filed: 07/25/2007
• Published: 01/29/2009
• Est. Priority Date: 07/25/2007
• Status: Active Grant

• Current Assignee: AgigA Tech Incorporated (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Sartore, Ronald H.
• Granted Patent: US 7,865,679 B2
• Time in Patent Office: Days
• US Class Current: 711/162
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 5/144 Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory subsystem includes volatile memory and nonvolatile memory, and logic to interrupt a power down save operation of the memory subsystem upon detection of a restoration of system power, and to enable use of the memory subsystem by the system if sufficient nonvolatile memory capacity of the memory subsystem is available to backup an amount of the volatile memory capacity of the memory subsystem.

Claims

1. A memory subsystem for use in a system, the memory subsystem comprising volatile memory and nonvolatile memory, the memory subsystem further comprising:

logic to interrupt a power down save operation of the memory subsystem upon detection of a restoration of system power, and to enable use of the memory subsystem by the system if sufficient nonvolatile memory capacity of the memory subsystem is available to backup an amount of the volatile memory capacity of the memory subsystem.

2. The memory subsystem of claim 1, wherein the logic to enable use of the memory subsystem by the system further comprises:

signaling the external system that the memory subsystem is available for use.

3. The memory subsystem of claim 1, wherein the logic to enable use of the memory subsystem by the system further comprises:

providing a status indication available for reading by the external system.

4. The memory subsystem of claim 1, wherein the logic to enable use of the memory subsystem by the system further comprises:

logic to erase sufficient dirty nonvolatile memory to backup the amount of volatile memory capacity.

5. The memory subsystem of claim 1, wherein the logic to enable use of the memory subsystem by the system further comprises:

logic to enable use of the memory subsystem by the system without delay if, when the power down save operation of the memory subsystem is interrupted by restoration of system power, sufficient nonvolatile memory capacity is already available to backup the amount of volatile memory capacity.

6. The memory subsystem of claim 1, further comprising:

logic to terminate a data backup from volatile memory of the memory subsystem to nonvolatile memory of the memory subsystem if system power is restored before the data backup is completed.

7. The memory subsystem of claim 1, further comprising:

logic to erase sufficient dirty nonvolatile memory to backup the amount of volatile memory capacity before enabling use of the memory subsystem by the system, and in, the event that external system power fails before enabling use of the memory subsystem, to backup at least portions of the volatile memory having data corresponding to data erased from the nonvolatile memory.

8. The memory subsystem of claim 7, wherein the logic to backup at least portions of the volatile memory having data corresponding to data erased from the nonvolatile memory further comprises:

logic to burst refresh the volatile memory for a time at least equal to a worst-case nonvolatile page preparation time, to place the volatile memory into a lower than fully operational power state while a new nonvolatile memory page is prepared and written, and to restore the volatile memory to a fully operational power state after the new nonvolatile memory page is prepared and written.

9. The memory subsystem of claim 1, further comprising:

logic to restore data from the nonvolatile memory to the volatile memory after restoration of system power and before ensuring that sufficient nonvolatile memory capacity of the memory subsystem is available to backup the amount of volatile memory capacity.

10. The memory subsystem of claim 9, wherein the logic to restore data from the nonvolatile memory to the volatile memory after restoration of system power further comprises:

logic to restore the data from the nonvolatile memory to the volatile memory after restoration of system power only if the restoration of system power did not interrupt a power down save operation of the memory subsystem.

11. A method in a memory subsystem disposed in a system, the memory subsystem comprising volatile memory and nonvolatile memory, the method comprising:

the memory subsystem interrupting a power down save operation of the memory subsystem upon detection of a restoration of system power; and

the memory subsystem enabling use of the memory subsystem by the system if sufficient nonvolatile memory capacity of the memory subsystem is available to backup an amount of the volatile memory capacity of the memory subsystem.

12. The method of claim 11, wherein the memory subsystem enabling use of the memory subsystem by the system further comprises:

erasing sufficient dirty nonvolatile memory to backup the amount of volatile memory capacity.

13. The method of claim 11, further comprising:

terminating a data backup from volatile memory of the memory subsystem to nonvolatile memory of the memory subsystem if system power is restored before the data backup is completed.

14. The method of claim 11, further comprising:

erasing sufficient dirty nonvolatile memory to backup the amount of volatile memory capacity before enabling use of the memory subsystem by the system, and in the event that system power fails before enabling use of the memory subsystem, to backup at least portions of the volatile memory having data corresponding to data erased from the nonvolatile memory.

15. The method claim 11, further comprising:

restoring data from the nonvolatile memory to the volatile memory after restoration of system power and before ensuring that sufficient nonvolatile memory capacity of the memory subsystem is available to backup an amount of volatile memory capacity.

16. The method of claim 15, wherein restoring data from the nonvolatile memory to the volatile memory after restoration of system power further comprises:

restoring the data from the nonvolatile memory to the volatile memory after restoration of system power only if the restoration of system power did not interrupt a power down save operation of the memory subsystem.

17. A device comprising:

a processor; and

a memory subsystem comprising volatile memory and nonvolatile memory addressable by the processor, the memory subsystem comprising logic to interrupt a power down save operation of the memory subsystem upon detection of a restoration of system power, and to enable use of the memory subsystem by the processor if sufficient nonvolatile memory capacity of the memory subsystem is available to backup an amount of the volatile memory capacity of the memory subsystem.

18. The device of claim 17, wherein the logic to enable use of the memory subsystem by the processor further comprises:

logic to signal the processor that the memory subsystem is available for use.

19. The device of claim 17, wherein the logic to enable use of the memory subsystem by the processor further comprises:

logic to provide a status indication available for reading by the processor.

20. The device of claim 17, wherein the logic to enable use of the memory subsystem by the processor further comprises:

logic to erase sufficient dirty nonvolatile memory to backup the amount of volatile memory capacity.