ERROR CORRECTING CODE GENERATION METHOD AND MEMORY CONTROL APPARATUS
First Claim
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1. An error correcting code generation method, comprising:
- storing data to be stored in a store instruction in a buffer;
searching a cache memory to perform a judgment as to whether or not the data to be stored exists in the cache memory;
when the data to be stored exists in the cache memory according to the judgment, generating a first error correcting code on the basis of data other than the data to be stored that was read out from the cache memory with the search of the cache memory, and keeping the generated first error correcting code;
generating a second error correcting code on the basis of the data to be stored in the buffer; and
generating an error correcting code for the data by merging the first error correcting code and the second error correcting code.
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Abstract
An objective of the present invention is to make it possible to appropriately correct an error of data in a cache memory. A store processing unit generates an nt-ECC on the basis of data stored in a non-target area that was read out from a cache memory with a search of the cache memory, and generates t-ECC on the basis of the data to be stored in the buffer.
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Citations
15 Claims
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1. An error correcting code generation method, comprising:
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storing data to be stored in a store instruction in a buffer; searching a cache memory to perform a judgment as to whether or not the data to be stored exists in the cache memory; when the data to be stored exists in the cache memory according to the judgment, generating a first error correcting code on the basis of data other than the data to be stored that was read out from the cache memory with the search of the cache memory, and keeping the generated first error correcting code; generating a second error correcting code on the basis of the data to be stored in the buffer; and generating an error correcting code for the data by merging the first error correcting code and the second error correcting code. - View Dependent Claims (2, 3, 4, 5)
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6. A memory control apparatus comprising:
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a buffer for storing data specified by a store instruction, a judgment circuit for searching a cache memory to judge whether or not the data to be stored in the store instruction exists in the cache memory; a first error correcting code generation circuit for, when the data to be stored exists in the cache memory according to the judgment performed by the judgment circuit, generating a first error correcting code on the basis of data other than the data to be stored that was read out from the cache memory with the search of the cache memory and keeping the generated first error correcting code; a second error correcting code generation circuit for generating a second error correcting code on the basis of the data to be stored in the buffer; and a merge circuit generating an error correcting code for the data by merging the first error correcting code and the second error correcting code. - View Dependent Claims (7, 8, 9, 10)
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11. A computer-readable storage medium on which is recorded a program for causing a computer to execute a process generating an error correcting code, said process comprising:
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storing data to be stored in a store instruction in a buffer; searching a cache memory to perform a judgment as to whether or not the data to be stored exists in the cache memory; when the data to be stored exists in the cache memory according to the judgment, generating a first error correcting code on the basis of the data other than the data to be stored that was read out from the cache memory with the search of the cache memory, and keeping the generated first error correcting code; generating a second error correcting code on the basis of the data to be stored in the buffer; and generating an error correcting code for the data by merging the first error correcting code and the second error correcting code. - View Dependent Claims (12, 13, 14, 15)
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Specification