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ANALYTICAL GLOBAL PLACEMENT FOR AN INTEGRATED CIRCUIT

  • US 20090031269A1
  • Filed: 07/07/2008
  • Published: 01/29/2009
  • Est. Priority Date: 07/27/2007
  • Status: Active Grant
First Claim
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1. A method for specifying positions of cell instances to be interconnected by nets within an integrated circuit (IC) to be fabricated, the IC having defined legal and illegal positions for cell instances, the method comprising the steps of:

  • a. generating a global placement plan specifying positions for the cell instances within the IC;

    b. iteratively modifying the global placement plan to move specified cell instance positions in directions and by distances determined by analyzing the global placement plan and an objective function that is a function of the specified cell instance positions, wherein a portion of the specified cell instance positions are illegal positions;

    c. look-ahead legalizing the global placement plan produced at step b by modifying the global placement plan to reduce the portion of specified cell instance positions that are in illegal positions;

    d. modifying the objective function; and

    e. iteratively repeating steps b, c and d,

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