ANALYTICAL GLOBAL PLACEMENT FOR AN INTEGRATED CIRCUIT
First Claim
1. A method for specifying positions of cell instances to be interconnected by nets within an integrated circuit (IC) to be fabricated, the IC having defined legal and illegal positions for cell instances, the method comprising the steps of:
- a. generating a global placement plan specifying positions for the cell instances within the IC;
b. iteratively modifying the global placement plan to move specified cell instance positions in directions and by distances determined by analyzing the global placement plan and an objective function that is a function of the specified cell instance positions, wherein a portion of the specified cell instance positions are illegal positions;
c. look-ahead legalizing the global placement plan produced at step b by modifying the global placement plan to reduce the portion of specified cell instance positions that are in illegal positions;
d. modifying the objective function; and
e. iteratively repeating steps b, c and d,
3 Assignments
0 Petitions
Accused Products
Abstract
A placer produces a global placement plan specifying positions of cell instances to be interconnected by nets within an integrated circuit (IC) by initially clusterizing cell instances to form a pyramidal hierarchy of blocks and generating an initial global placement plan specifying a position of each block at a highest level of the hierarchy. The placer then declusterizes the global placement plan by replacing the highest level blocks with their component blocks and then improves the routability of the global placement plan by iteratively moving specified block positions in directions and by distances dynamically determined by analyzing the global placement plan and an objective function having a total wirelength term and having a bin density term reflecting density of blocks in specified areas (bins) of the IC. The placer iteratively repeats the declusterization and routability improvement process until the global placement plan specifies positions of all blocks residing at the lowest level of the hierarchy, with weighting of the bin density term adjusted when necessary during each iteration of the routability improvement process to provide sufficient white space in each bin. The placer employs a look-ahead legalization technique to move low level blocks to legal positions during later iterations of the plan improvement process.
38 Citations
16 Claims
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1. A method for specifying positions of cell instances to be interconnected by nets within an integrated circuit (IC) to be fabricated, the IC having defined legal and illegal positions for cell instances, the method comprising the steps of:
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a. generating a global placement plan specifying positions for the cell instances within the IC; b. iteratively modifying the global placement plan to move specified cell instance positions in directions and by distances determined by analyzing the global placement plan and an objective function that is a function of the specified cell instance positions, wherein a portion of the specified cell instance positions are illegal positions; c. look-ahead legalizing the global placement plan produced at step b by modifying the global placement plan to reduce the portion of specified cell instance positions that are in illegal positions; d. modifying the objective function; and e. iteratively repeating steps b, c and d, - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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Specification