SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
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Accused Products
Abstract
A semiconductor device and method of manufacture and, more particularly, a semiconductor device having strain films and a method of manufacture. The device includes an embedded SiGeC layer in source and drain regions of an NFET device and an embedded SiGe layer in source and drain regions of a PFET device. The PFET device is subject to compressive strain. The method includes embedding SiGe in source and drain regions of an NFET device and implanting carbon in the embedded SiGe forming an SiGeC layer in the source and drain regions of the NFET device. The SiGeC is melt laser annealed to uniformly distribute the carbon in the SiGeC layer, thereby counteracting a strain generated by the embedded SiGe.
49 Citations
23 Claims
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1-20. -20. (canceled)
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21. A device comprising an embedded SiGeC layer in source and drain regions of an NFET device;
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an embedded SiGe layer in source and drain regions of a PFET device, wherein; the PFET device is subject to compressive strain; carbon is uniformly distributed in the embedded SiGeC layer in the source and drain regions of the NFET device; the carbon of the SiGeC counteracts compressive forces in the source and drain region of the NFET device; the carbon of the SiGeC does not extend into an underlying substrate of the NFET device; and the carbon of the SiGeC places the NFET device in a tensile strain.
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22. A CMOS device comprising embedded SiGeC in source and drain regions of an NFET and embedded SiGe in source and drain regions of a PFET, wherein:
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the PFET is placed under a compressive strain and the NFET is placed in one of a neutral state and a tensile strain; carbon is uniformly distributed in the embedded SiGeC layer in the source and drain regions of the NFET; the carbon of the SiGeC counteracts compressive forces in the source and drain region of the NFET; and the carbon of the SiGeC does not extend into an underlying substrate of the NFET device.
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23. A method, comprising:
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embedding SiGe in source and drain regions of an NFET device; implanting carbon in the embedded SiGe forming an SiGeC layer in the source and drain regions of the NFET device; and heating the SiGeC to uniformly distribute the carbon in the SiGeC layer, thereby counteracting a strain generated by the embedded SiGe, wherein; the heating is a melt laser anneal; the heating is below a melting point of an underlying substrate; and the carbon is implanted before or after a rapid thermal anneal of the source and drain regions of the NFET device; the method further comprising; embedding SiGe in source and drain regions of a PFET device and blocking the source and drain regions of the PFET device during the implanting step; and masking the PFET device with a same mask during the implanting step and implantation of the source and drain regions of the NFET device, wherein the embedding SiGe in the source and drain regions of the NFET device is performed at a same time as the embedding SiGe in the source and drain regions of the PFET device.
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Specification