Non-volatile memory cell and non-volatile memory device using said cell

• US 20090032862A1
• Filed: 10/31/2007
• Published: 02/05/2009
• Est. Priority Date: 08/01/1997
• Status: Abandoned Application

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Maayan, Eduardo
• Application Number:
  US11/979,187
• Publication Number:
  US 20090032862A1
• Time in Patent Office: Days
• US Class Current: 257/324
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation

Abstract

A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The non-conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near where the programming voltages were applied to. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and to either the right or the left region while the other region is grounded. Two bits are able to be programmed and read due to a combination of relatively low gate voltages with reading in the reverse direction. This greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region associated with each of the bits. In addition, both bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and either left or right regions so as to cause electrons to be removed from the corresponding charge trapping region of the nitride layer.

Claims

1. A method of fabricating a non-volatile memory cell comprising:

depositing a dielectric charge trapping layer substantially above at least a portion of a channel of the cell,

said charge trapping layer being adapted to be charged and discharged more than 100 cycles before degrading beyond an operable state.

2. The method according to claim 1, wherein said dielectric charge trapping layer is adapted to be charged and discharged more than 500 cycles before degrading beyond an operable state.

3. The method according to claim 1, wherein said dielectric charge trapping layer is adapted to be charged and discharged more than 2,000 cycles before degrading beyond an operable state.

4. The method according to claim 1, wherein said dielectric charge trapping layer is adapted to be charged and discharged more than 10,000 cycles before degrading beyond an operable state.

5. A non-volatile memory cell comprising:

a dielectric charge trapping layer located substantially above at least a portion of a channel of the cell,

said charge trapping layer being adapted to be charged and discharged more than 100 cycles before degrading beyond an operable state.

6. The non-volatile memory cell according to claim 5, wherein said dielectric charge trapping layer is adapted to be charged and discharged more than 500 cycles before degrading beyond an operable state.

7. The non-volatile memory cell according to claim 5, wherein said dielectric charge trapping layer is adapted to be charged and discharged more than 2,000 cycles before degrading beyond an operable state.

8. The non-volatile memory cell according to claim 6, wherein said dielectric charge trapping layer is adapted to be charged and discharged more than 10,000 cycles before degrading beyond an operable state.

9. A non-volatile memory cell comprising:

a charge trapping layer comprised of an impure silicon based dielectric located substantially above a channel of the cell,

wherein said silicon based dielectric contains an impurity selected from the group consisting of oxygen, nitrogen, boron, carbon and polycrystalline silicon.

10. The cell according to claim 9, wherein said impurity is adapted to inhibit charge migration.

11. The cell according to claim 9, wherein said dielectric has a thickness of between approximately 20 and 100 angstroms.

12. The cell according to claim 9, wherein a layer of oxide is located at least partially between said charge trapping layer and said channel.

13. A non-volatile memory cell comprising:

a silicon based dielectric charge trapping layer having a thickness of between approximately 20 and 100 angstroms, at least a portion of said layer located substantially above a channel of the cell; and

an oxide layer substantially between at least a portion of said charge trapping layer and said channel.

14. The cell according to claim 13, wherein a thickness of said oxide layer is 60 angstroms or greater.

15. The cell according to claim 13, wherein a thickness of said charge trapping layer compared to a thickness of said oxide layer is between approximately 0.6 and 5.

16. The cell according to claim 13, wherein said dielectric layer is adulterated.

17. The cell according to claim 13, wherein oxygen adulterates said dielectric layer.

18. The cell according to claim 16, wherein the adulterated dielectric layer is enhanced.

19. A non-volatile memory cell comprising:

a charge trapping region at least partially including silicon nitride, located substantially below a gate of said cell and having a thickness of between approximately 20 and 100 angstroms, and wherein at least a portion of said charge trapping region is located substantially above an oxide.

20. The cell according to claim 19, wherein said oxide includes silicon oxide or silicon dioxide.

21. The cell according to claim 19, wherein said charge trapping region is at least partially located below a second oxide.

22. The cell according to claim 21, wherein said oxide includes silicon oxide or silicon dioxide.

23. The cell according to claim 19, wherein said charge trapping region is adulterated with oxygen.

24. The cell according to claim 19, wherein a thickness of said charge trapping region compared to a thickness of said oxide is between approximately 0.6 and 5.