Integrated circuit design based on scan design technology

• US 20090032899A1
• Filed: 07/28/2008
• Published: 02/05/2009
• Est. Priority Date: 07/31/2007
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Irie, Kazuyuki
• Granted Patent: US 7,919,981 B2
• Time in Patent Office: Days
• US Class Current: 257/499
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/35 Delay-insensitive circuit design, e.g. asynchronous or self-timed

Abstract

An integrated circuit is provided with a scan chain including a scan flip-flop and a dummy block. The dummy block has a clock terminal receiving a clock signal, a scan input terminal connected to a scan data line within the scan chain, and a scan output terminal connected to another scan data line within the scan chain. The dummy block is configured to output data on the scan output terminal in response to input data fed to the scan input terminal, not responsively to the clock signal.

Claims

1. An integrated circuit comprising:

a scan chain including a scan flip-flop and a dummy block,

wherein said dummy block has a clock terminal receiving a clock signal, a scan input terminal connected to a scan data line within said scan chain, and a scan output terminal connected to another scan data line within said scan chain, and

wherein said dummy block is configured to output data on said scan output terminal in response to input data fed to said scan input terminal, not responsively to said clock signal.

2. The integrated circuit according to claim 1, wherein said dummy block includes a through path connected between said scan input terminal and said scan output terminal.

3. The integrated circuit according to claim 2, wherein said through path comprises a combination circuit connected between said scan input terminal and said scan output terminal.

4. The integrated circuit according to claim 1, wherein said dummy block further includes a block terminal which is not connected to any interconnection outside said dummy block.

5. The integrated circuit according to claim 4, wherein said clock terminal and said block terminal are not connected to any interconnection within said dummy block.

6. The integrated circuit according to claim 1, wherein said scan flip-flop has a clock terminal receiving said clock signal, a scan input terminal, and a scan output terminal, and

wherein a positional relation among said clock terminal, said scan input terminal, and said scan output terminal in said dummy block is same as a positional relation among said clock terminal, said scan input terminal, and said scan output terminal in said scan flip-flop.

7. The integrated circuit according to claim 1, wherein said scan flip-flop has a clock terminal receiving said clock signal, and

wherein an input capacitance of said clock terminal is equal to that of said clock terminal of said dummy block.

8. The integrated circuit according to claim 1, wherein said dummy block has a same size as said scan flip-flop.

9. The integrated circuit according to claim 1, wherein said scan flip-flop and said dummy block includes transistors in a lower layer, and

wherein a transistor structure of said dummy block is same as that of said scan flip-flop.

10. An integrated circuit design method comprising:

placing cells including a scan flip-flop cell and a dummy block cell;

implementing clock tree synthesis for said scan flip-flop cell and said dummy block cell; and

implementing routing for said cells so that a scan chain including said scan flip-flop and said dummy block cell is formed,

wherein said dummy block cell has a clock terminal receiving a clock signal, a scan input terminal connected to a scan data line within said scan chain, and a scan output terminal connected to another scan data line within said scan chain,

wherein said dummy block cell is configured to output data on said scan output terminal in response to input data fed to said scan input terminal, not responsively to said clock signal.

11. The integrated circuit design method according to claim 10, wherein said dummy block cell additionally has a block terminal, and

wherein said block terminal is not connected to any interconnections outside said dummy block cell in said routing.

12. The integrated circuit design method according to claim 11, wherein said clock terminal and said block terminal are not connected to any interconnection within said dummy block cell.

13. The integrated circuit design method according to claim 10, further comprising:

replacing said dummy block cell with an additional scan flip-flop cell,

wherein said dummy block cell has a same size as said additional scan flip-flop cell,

wherein said additional scan flip-flop cell has a clock terminal receiving said clock signal, a scan input terminal and a scan output terminal, and

wherein a positional relation among said clock terminal, said scan input terminal, and said scan output terminal in said dummy block cell is same as a positional relation among said clock terminal, said scan input terminal, and said scan output terminal in said additional scan flip-flop cell.

14. The integrated circuit design method according to claim 13, wherein an input capacitance of said clock terminal of said dummy block cell is equal to an input capacitance of said clock terminal of said additional scan flip-flop cell, and

wherein clock tree synthesis is not implemented again after said replacing.

15. The integrated circuit design method according to claim 10, wherein said scan flip-flop and said dummy block includes transistors in a lower layer,

wherein a transistor structure of said dummy block is same as that of said scan flip-flop, and

wherein said integrated circuit design method further comprises rerouting interconnections in an upper layer positioned above said lower layer so that said dummy block cell operates identically to said scan flip-flop cell.