MULTIPLE VOLTAGE INTEGRATED CIRCUIT AND DESIGN METHOD THEREFOR

• US 20090032903A1
• Filed: 10/14/2008
• Published: 02/05/2009
• Est. Priority Date: 11/24/2003
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Lamb, Douglass T., Puri, Ruchir, Wallach, David, Correale, Anthony JR., Kung, David S., Pan, Zhigang
• Application Number:
  US12/251,195
• Publication Number:
  US 20090032903A1
• Time in Patent Office: Days
• US Class Current: 257/510
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits

Abstract

An integrated circuit (IC) design, method and program product for reducing IC design power consumption. The IC is organized in circuit rows. Circuit rows may include a low voltage island powered by a low voltage (V_ddl) supply and a high voltage island powered by a high voltage (V_ddh) supply. Circuit elements including cells, latches and macros are placed with high or low voltage islands to minimize IC power while maintaining overall performance. Level converters may be placed with high voltage circuit elements.

Claims

1. An integrated circuit (IC) comprising:

a plurality of circuit rows, at least one row of said plurality of circuit rows including three or more voltage islands;

at least one low voltage island in said at least one row, circuit elements in each said at least one low voltage island being powered by a low voltage (V_ddl) supply; and

at least one high voltage island in said at least one row, circuit elements in each said at least one high voltage island being powered by a high voltage (V_ddh) supply, V_ddh being a higher voltage than V_ddl.