REDISTRIBUTED CHIP PACKAGING WITH THERMAL CONTACT TO DEVICE BACKSIDE

• US 20090032933A1
• Filed: 07/31/2007
• Published: 02/05/2009
• Est. Priority Date: 07/31/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Lee, Tien Yu T., Frear, Darrel R., Maalouf, Elie A., Griffiths, James R., Keser, Lizabeth Ann A., Tracht, Neil T.
• Granted Patent: US 8,217,511 B2
• Time in Patent Office: Days
• US Class Current: 257/693
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Redistributed Chip Packaging with Thermal Contact to Device Backside An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.

Claims

1. An integrated circuit assembly, comprising:

a panel including a device at least partially surrounded by an encapsulant wherein an upper surface of the panel includes an active surface of the device;

a layer of interconnect overlying the upper surface of the panel, the interconnect layer including an insulating film having contacts formed therein an interconnect metallization formed thereon;

wherein a lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab, wherein an upper surface of the slab is in thermal contact with the backside of the device.

2. The assembly of claim 1, further comprising a set of panel vias located within portions of the encapsulant wherein the panel vias comprise an electrical and thermal conductor extending from the upper surface of the panel to the lower surface of the panel.

3. The assembly of claim 2, wherein the panel lacks wirebonds and wherein electrical connections between the active surface of the device and an underlying circuit board traverse the interconnect metallization and the panel vias.

4. The assembly of claim 2, further comprising an external device attached to a bond pad overlying a topmost interconnect layer wherein the external device is in electrical contact with an underlying circuit board through the interconnect layers and the panel vias.

5. The assembly of claim 1, wherein the slab comprises a substantially uniform and continuous metal.

6. The assembly of claim 1, wherein the lower surface of the panel is in thermal contact with a land grid array (LGA) pad of an underlying circuit board.

7. The assembly of claim 1, wherein the device is a power amplifier device.

8. The assembly of claim 7, wherein the backside of the device comprises gallium arsenide or silicon carbide.

9. An integrated circuit assembly method, comprising:

forming a panel by forming an encapsulant at least partially surrounding a device, wherein an upper surface of the panel is substantially coplanar with an active surface of the device;

forming a set of panel vias in the panel, the thermal vias extending from an upper surface to a lower surface of the panel, wherein the panel vias comprise an electrically and thermally conductive material; and

forming at least one interconnect layer overlying the panel wherein the interconnect layer includes an insulating film and an interconnect metallization.

10. The method of claim 9, further comprising, prior to forming the panel, removing a portion of a substrate portion of the device to thin the device.

11. The method of claim 9, further comprising, prior to forming the encapsulant, forming a thermal slab in thermal contact with the backside of the device, wherein the thermal slab comprises at least one thermally and electrically conductive metal.

12. The method of claim 11, wherein a lower surface of the panel is substantially coplanar with a lower surface of the thermal slab.

13. The method of claim 9, further comprising:

prior to forming the encapsulant, affixing the active surface of the device to a carrier plate with an adhesive layer; and

after forming the encapsulant, removing the carrier plate and the adhesive layer.

14. The method of claim 9, further comprising attaching the integrated circuit assembly to a printed circuit board (PCB) wherein the integrated circuit assembly overlies the PCB with the panel lower surface proximal to the PCB and the panel upper surface distal from the PCB.

15. The method of claim 14, wherein the panel lower surface is substantially coplanar with either a backside of the device or a lower surface of a thermally conductive slab having an upper surface in thermal contact with the backside of the device.

16. The method of claim 14, wherein said attaching of the assembly to the PCB includes attaching the panel to land grid array (LGA) pads of the PCB.

17. The method of claim 9, further comprising attaching at least one external device overlying an uppermost interconnect layer.

18. The method of claim 9, further comprising forming a shielding metallization layer overlying an uppermost interconnect layer, wherein the shielding metallization layer comprises a substantially continuous plane of metallization overlying the panel.

19. An integrated circuit assembly, comprising:

a printed circuit board (PCB);

a panel overlying the PCB, wherein the panel includes an integrated circuit device at least partially surrounded by an encapsulant wherein an active surface of the device is coplanar with an upper surface of the panel and a backside of the device is in thermal contact with a structure selected from the PCB or an upper surface of a thermal slab having a lower surface in thermal contact with the PCB; and

an interconnect layer overlying the panel wherein said interconnect layer includes an insulating film having contacts formed therein and interconnect metallization formed thereon.

20. The assembly of claim 19, further comprising a set of panel vias, wherein the panel vias comprise thermal and electrical conduits extending through the panel between the interconnect layer suitable for bonding with a contact pad of an underlying circuit board.