REDISTRIBUTED CHIP PACKAGING WITH THERMAL CONTACT TO DEVICE BACKSIDE
First Claim
1. An integrated circuit assembly, comprising:
- a panel including a device at least partially surrounded by an encapsulant wherein an upper surface of the panel includes an active surface of the device;
a layer of interconnect overlying the upper surface of the panel, the interconnect layer including an insulating film having contacts formed therein an interconnect metallization formed thereon;
wherein a lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab, wherein an upper surface of the slab is in thermal contact with the backside of the device.
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Accused Products
Abstract
Redistributed Chip Packaging with Thermal Contact to Device Backside An integrated circuit assembly includes a panel including an semiconductor device at least partially surrounded by an encapsulant. A panel upper surface and a device active surface are substantially coplanar. The assembly further includes one or more interconnect layers overlying the panel upper surface. Each of the interconnect layers includes an insulating film having contacts formed therein an interconnect metallization formed thereon. A lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab that has an upper surface in thermal contact with the device backside. The assembly may also include a set of panel vias. The panel vias are thermally and electrically conductive conduits extending through the panel between the interconnect layer and suitable for bonding with a land grid array (LGA) or other contact structure of an underlying circuit board.
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Citations
20 Claims
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1. An integrated circuit assembly, comprising:
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a panel including a device at least partially surrounded by an encapsulant wherein an upper surface of the panel includes an active surface of the device; a layer of interconnect overlying the upper surface of the panel, the interconnect layer including an insulating film having contacts formed therein an interconnect metallization formed thereon; wherein a lower surface of the panel is substantially coplanar with either a backside of the device or a lower surface of a thermally and electrically conductive slab, wherein an upper surface of the slab is in thermal contact with the backside of the device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit assembly method, comprising:
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forming a panel by forming an encapsulant at least partially surrounding a device, wherein an upper surface of the panel is substantially coplanar with an active surface of the device; forming a set of panel vias in the panel, the thermal vias extending from an upper surface to a lower surface of the panel, wherein the panel vias comprise an electrically and thermally conductive material; and forming at least one interconnect layer overlying the panel wherein the interconnect layer includes an insulating film and an interconnect metallization. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. An integrated circuit assembly, comprising:
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a printed circuit board (PCB); a panel overlying the PCB, wherein the panel includes an integrated circuit device at least partially surrounded by an encapsulant wherein an active surface of the device is coplanar with an upper surface of the panel and a backside of the device is in thermal contact with a structure selected from the PCB or an upper surface of a thermal slab having a lower surface in thermal contact with the PCB; and an interconnect layer overlying the panel wherein said interconnect layer includes an insulating film having contacts formed therein and interconnect metallization formed thereon. - View Dependent Claims (20)
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Specification