Small Area, Robust Silicon Via Structure and Process

• US 20090032951A1
• Filed: 08/02/2007
• Published: 02/05/2009
• Est. Priority Date: 08/02/2007
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cotte, John M., Knickerbocker, John Ulrich, Andry, Paul S., Tsang, Cornelia K.
• Granted Patent: US 7,902,069 B2
• Time in Patent Office: Days
• US Class Current: 257/751
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/80 Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01072 Hafnium [Hf]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A semiconductor structure includes: at least one silicon surface wherein the surface can be a substrate, wafer or other device. The structure further includes at least one electronic circuit formed on each side of the at least one surface; and at least one conductive high aspect ratio through silicon via running through the at least one surface. Each through silicon via is fabricated from at least one etch step and includes: at least one thermal oxide dielectric for coating at least some of a sidewall of the through silicon via for a later etch stop in fabrication of the through silicon via.

Claims

14. A method for etching a plurality of deep vias on a substrate, the method comprising:

prefabricating a thermal oxide collar using an etching process for creating one or more etches on a silicon substrate;

adding one or more circuits to the substrate through the etches;

creating conductive vias in the substrate by deepening the etches;

depositing a liner contact on the substrate;

applying a chemical-mechanical planarization as touchup and removing the liner contact;

building a back end of line layer;

grinding the liner; and

depositing an insulator.

1. A semiconductor structure comprising:

at least one silicon surface;

at least one electronic circuit formed on each side of the at least one surface;

at least one conductive high aspect ratio through silicon via disposed through the at least one surface, each through silicon via being fabricated from at least one etch step, and comprising;

at least one thermal oxide dielectric for coating at least some of a sidewall of the through silicon via for a later etch stop in fabrication of the through silicon via.

2. The semiconductor structure of claim 1, wherein the through silicon via comprises tungsten.

3. The semiconductor structure of claim 2, wherein the through silicon via further comprises polysilicon.

4. The semiconductor structure of claim 1, wherein the through silicon via comprises copper.

5. The semiconductor structure of claim 4, wherein the through silicon via further comprises polysilicon.

6. The semiconductor structure of claim 1 wherein the through silicon via has a width ranging from 0.2 to 8 microns.

7. The semiconductor structure of claim 1 wherein the at least one electronic circuit comprises active circuits.

8. The semiconductor structure of claim 1 wherein the at least one electronic circuit comprises passive circuits.

9. The semiconductor structure of claim 1 wherein the at least one through silicon via comprises an annular shape.

10. The semiconductor structure of claim 9 wherein the annular shape comprises a double annular configuration.

11. The semiconductor structure of claim 1 wherein the at least one through silicon via has a depth of approximately 2 to 150 microns.

12. The semiconductor structure of claim 1 wherein the at least one silicon surface is a wafer.

13. The semiconductor structure of claim 1 wherein the at least one silicon surface is a substrate.

15. The method of claim 14 wherein prefabricating a thermal oxide collar comprises:

applying a thermal oxide coating to the silicon substrate such that thermal oxide coats sidewalls of the etches; and

applying oxide over an inner diameter of each of the etches.

16. The method of claim 14 further wherein a deep reactive ion etching process is used to prefabricate the thermal oxide collar.

17. The method of claim 14 further comprising:

applying solder to the substrate using a ball limiting metallurgy.

18. The method of claim 14 wherein the liner contact is deposited on a backside of the substrate.

19. The method of claim 14 further comprising depositing a liner contact in each of the etches.

20. The method of claim 19 wherein the liner contact comprises tungsten.

21. The method of claim 20 wherein the liner contact further comprises polysilicon.

22. The method of claim 19 wherein the liner contact comprises copper.

23. The method of claim 22 wherein the liner contact further comprises polysilicon.

24. The method of claim 14 wherein creating conductive vias is done from a backside of the substrate.

25. The method of claim 14 further comprising wiring circuits on the substrate.

26. The method of claim 14 wherein depositing an insulator comprises depositing oxide.

21-1. The method of claim 15, wherein the etches are annular.

27. A method for etching deep vias on a substrate, the method comprising:

prefabricating a thermal oxide collar using an etching process for creating the deep vias on a silicon substrate, wherein etch stops are created;

adding metallization structures as conductors;

performing wafer thinning;

removing any surface oxide and silicon using the etch stops as barriers;

depositing a liner/barrier;

plating the conductors; and

forming an interconnection pad.

28. The method of claim 27 wherein prefabricating a thermal oxide collar comprises:

applying a thermal oxide coating to the silicon substrate such that thermal oxide coats sidewalls of the etches; and

applying oxide over an inner diameter of each of the etches.

29. The method of claim 27 wherein forming an interconnection pad comprises forming a ball limiting metallurgy pad comprising solder balls.

30. The method of claim 27 wherein adding metallization structures comprises performing back end of line processing.

31. The method of claim 27 wherein adding metallization structures comprises performing front end of line processing.

32. The method of claim 28 wherein depositing a liner/barrier further comprises:

depositing tungsten in the deep vias for reducing mechanical stress.

33. The method of claim 32 further comprising:

depositing polysilicon in the deep vias.

34. The method of claim 28 wherein depositing a liner/barrier further comprises:

depositing copper in the deep vias for reducing mechanical stress.

35. The method of claim 34 further comprising:

depositing polysilicon in the deep vias.