SEMICONDUCTOR STRUCTURES INCLUDING TIGHT PITCH CONTACTS AND METHODS TO FORM SAME

• US 20090032963A1
• Filed: 08/03/2007
• Published: 02/05/2009
• Est. Priority Date: 08/03/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tran, Luan C.
• Granted Patent: US 8,481,417 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/31608 Deposition of SiO2 H01L21/31625, H01L21/31629 and H01L21/31633 take precedence
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices

Abstract

Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.

Claims

1. A semiconductor structure comprising a plurality of tight pitch conductive lines each integrally formed with a conductive contact of a plurality of tight pitch conductive contacts.

2. The semiconductor structure of claim 1, wherein the plurality of tight pitch conductive contacts comprise a plurality of conductive vias.

3. The semiconductor structure of claim 2, wherein each conductive via of the plurality of conductive vias extends from one tight pitch conductive line of the plurality of tight pitch conductive lines to a tight pitch active area on a semiconductor substrate.

4. The semiconductor structure of claim 2, wherein the active area comprises at least a portion of a feature selected from the group consisting of a source, a drain, a gate, a conductive pad and a conductive trace.

5. The semiconductor structure of claim 1, wherein the tight pitch conductive lines and the tight pitch conductive contacts each have a width of less than about 50 nm.

6. The semiconductor structure of claim 1, wherein the tight pitch conductive lines and the tight pitch conductive contacts each have a width of less than about 30 nm.

7. The semiconductor structure of claim 1, wherein each integrally formed tight pitch conductive line and tight pitch conductive contact comprises a unitary mass of at least one of tungsten, copper, aluminum, and nickel.

8. The semiconductor structure of claim 1, wherein the plurality of tight pitch conductive lines extend in a direction substantially parallel to one another.

9. A method of fabricating a semiconductor structure, the method comprising:

substantially concurrently forming a plurality of tight pitch conductive lines and a plurality of tight pitch conductive contacts; and

integrally forming each tight pitch conductive line of the plurality of tight pitch conductive lines with one tight pitch conductive contact of the plurality of tight pitch conductive contacts.

10. The method of claim 9, further comprising providing electrical contact between each tight pitch conductive contact and a corresponding tight pitch active area of a plurality of tight pitch active areas on a surface of a semiconductor substrate.

11. The method of claim 9, further comprising:

forming a first layer of dielectric material;

forming a mask layer over the first layer of dielectric material;

providing an aperture through the mask layer to the first layer of dielectric material;

forming a second layer of dielectric material over the mask layer and the aperture;

forming a plurality of tight pitch trenches in the second layer of dielectric material; and

forming a plurality of tight pitch contact holes in the first layer of dielectric material through the aperture in the mask layer.

12. The method of claim 11, further comprising sequentially forming the plurality of tight pitch trenches in the second layer of dielectric material and the plurality of tight pitch trenches in the first layer of dielectric material using a single etching process.

13. The method of claim 11, wherein using a single etching process comprises using an anisotropic plasma etching process.

14. The method of claim 13, further comprising causing at least one of the first layer of dielectric material and the second layer of dielectric material to exhibit a variable etch rate during the anisotropic plasma etching process.

15. The method of claim 14, further comprising doping the at least one of the first layer of dielectric material and the second layer of dielectric material with a dopant and causing the concentration of the dopant within the at least one of the first layer of dielectric material and the second layer of dielectric material to vary across a thickness of the at least one of the first layer of dielectric material and the second layer of dielectric material.

16. The method of claim 11, further comprising forming a plurality of tight pitch spacers over the second layer of dielectric material, and etching the first layer of dielectric material through the plurality of spacers to form the plurality of tight pitch trenches.

17. The method of claim 11, wherein at least one of forming the plurality of tight pitch trenches and forming the plurality of tight pitch contact holes comprises at least one of a pitch multiplication process, a double-patterning process, a double exposure process, a maskless photolithography process, and an advanced fine line lithography process.

18. The method of claim 11, further comprising:

providing conductive material in each tight pitch trench of the plurality of tight pitch trenches to form the plurality of tight pitch conductive lines; and

providing the conductive material in each tight pitch contact hole of the plurality of tight pitch contact holes to form the plurality of tight pitch conductive contacts.

19. The method of claim 18, further comprising substantially concurrently introducing conductive material into each tight pitch trench of the plurality of tight pitch trenches and each tight pitch contact hole of the plurality of tight pitch contact holes.

20. The method of claim 18, further comprising selecting the conductive material to comprise at least one of tungsten, copper, aluminum, and nickel.

21. A semiconductor structure comprising:

a semiconductor substrate comprising a plurality of tight pitch active areas;

a plurality of tight pitch conductive lines extending laterally over the semiconductor substrate; and

a plurality of tight pitch conductive contacts each extending from one conductive line of the plurality of conductive lines through an aperture in a mask layer to one tight pitch active area of the plurality of tight pitch active areas.

22. The semiconductor structure of claim 21, wherein each tight pitch conductive line of the plurality of tight pitch conductive lines is integrally formed with a corresponding one tight pitch conductive contact of the plurality of tight pitch conductive contacts.

23. The semiconductor structure of claim 21, wherein each tight pitch contact of the plurality of tight pitch conductive contacts extends through a common aperture in the mask layer.

24. The semiconductor structure of claim 23, wherein the common aperture in the mask layer is elongated and extends in a lateral direction over the semiconductor substrate in a direction generally perpendicular to the plurality of tight pitch conductive lines.

25. A method of forming a semiconductor device, comprising:

forming a first layer of material over a plurality of features on a semiconductor substrate having a tight pitch;

forming a first mask having at least one aperture over the first layer of material;

forming a second layer of material over the first mask;

forming a second mask having a plurality of apertures having a tight pitch over the second layer of material;

etching the second layer of material and the first layer of material through the plurality of apertures of the second mask and the at least one aperture of the first mask to form a plurality of trenches in the second layer of material and a plurality of holes in the first layer of material; and

filling the plurality of holes and the plurality of trenches with a conductive material to form a plurality of integral conductive structures having a tight pitch, each conductive structure of the plurality of conductive structures electrically contacting a feature of the plurality of features on the semiconductor substrate.

26. The method of claim 25, forming a second mask comprises using a spacer etch process to form the plurality of apertures in the second mask.

27. The method of claim 25, further comprising selectively doping at least one of the first layer of material and the second layer of material to form a graded dopant concentration therein.

28. The method of claim 27, further comprising selectively tailoring a gradient of the dopant concentration to control an etch rate of the at least one of the first layer of material and the second layer of material with respect to an etchant.