METHOD OF DIGITAL EXTRACTION FOR ACCURATE FAILURE DIAGNOSIS
First Claim
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1. A method for testing VLSI circuits comprising the steps of:
- generating a set of test patterns for an original circuit;
running a test on the original circuit utilizing the generated test patterns and identifying faulty nets within the circuit;
providing an extraction algorithm;
extracting a subset of the original circuit for failure diagnosis utilizing the provided extraction algorithm;
the extracting step further comprising the step of eliminating unnecessary circuit elements from the original circuit; and
testing the extracted subset to diagnose reasons for failure of the identified faulty nets.
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Abstract
A method for testing VLSI circuits comprises a two-pass diagnostic method for testing a circuit wherein a first pass comprises a conventional test flow wherein an ATPG tool generates a set of test patterns and identifies possible faulty nets within the circuit. A second pass focuses on a designated critical subset of the circuit extracted using a method for extracting a subset for failure diagnosis of the tested circuit. A second pass utilizes an extraction algorithm which extracts one or more critical subsets of the circuit in order to obtain more accurate failure diagnosis.
18 Citations
11 Claims
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1. A method for testing VLSI circuits comprising the steps of:
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generating a set of test patterns for an original circuit; running a test on the original circuit utilizing the generated test patterns and identifying faulty nets within the circuit; providing an extraction algorithm; extracting a subset of the original circuit for failure diagnosis utilizing the provided extraction algorithm; the extracting step further comprising the step of eliminating unnecessary circuit elements from the original circuit; and testing the extracted subset to diagnose reasons for failure of the identified faulty nets.
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2. A method for testing VLSI circuits comprising the steps of:
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generating a set of test patterns for an original circuit; running a test on the original circuit utilizing the generated test patterns and identifying faulty nets within the circuit; providing an extraction algorithm comprising a series of rules for eliminating unnecessary circuit elements from the original circuit; executing the rules of the extraction algorithm and thereby extracting a subset of the original circuit for failure diagnosis; and testing the extracted subset and thereby identifying a reduced number of faulty nets; and thereafter diagnosing root causes for failure of the original circuit.
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3. A method for extracting a critical subset circuit from an original circuit for performing failure diagnosis on identified faulty nets within the circuit comprising the steps of:
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providing an original circuit; providing an extraction algorithm comprising a series of rules for eliminating unnecessary circuit elements from the original circuit; defining a subset circuit within the original circuit containing all faulty nets and surrounding circuitry traced up to primary and pseudo primary inputs; extracting a reduced circuit from the defined subset; the reduced circuit comprising at least one complete path from one faulty site of one faulty net to the primary and pseudo primary inputs; and passing the reduced circuit through a pattern generation test tool for fault diagnosis of the one faulty net within the reduced circuit. - View Dependent Claims (4)
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5. A method for extracting a critical subset circuit from an original circuit for performing failure diagnosis on interested faulty nets within the circuit identified during previous testing operations comprising the steps of:
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defining critical paths for each identified net such that at each identified net comprises at least one unique complete path from the identified net to primary or pseudo primary inputs of the original circuit and at least one unique complete path to primary or pseudo primary outputs of the original circuit; assigning net values for all nets surrounding the identified nets; assigning net values for critical paths of the identified nets and surrounding critical paths; and eliminating nets and paths not associated with the identified nets.
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6. A method for testing VLSI circuits comprising hie steps of:
- generating a set of test patterns for an original circuit;
running a test on the original circuit utilizing the generated test patterns and identifying faulty nets within the circuit; providing an extraction algorithm comprising the steps of; a) providing a synthesized, full scan netlist of the original circuit; b) providing a possible candidate fault list which contains each existing fault within the circuit, each existing fault having a gate name and position; c) assigning net types to all nets within the original circuit, the net types selected from the group consisting of Core (C), extended (E), to be decided (D), can be passivated (P), and can be ignored (X); d) assigning net attributes for all type P and D nets; e) converting assigned type P and D nets to either type E or X nets; t) re-assigning net attributes to converted nets; and g) repeating steps e and i until all type D nets are converted to either type E or X nets and all P nets have net possibility attributes of “
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”extracting a reduced circuit from the defined subset according to the provided extraction algorithm, the reduced circuit comprising at least one complete path from one faulty site of one faulty net to the primary and pseudo primary inputs; and passing the reduced circuit through a pattern generation test tool for fault diagnosis of the one faulty net within the reduced circuit. - View Dependent Claims (7, 8, 9, 10)
- generating a set of test patterns for an original circuit;
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11. A method for fault diagnosing in VLSI circuits comprising the steps of:
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a) generating a set of test patterns for an original circuit; b) running a test on the original circuit utilizing the generated test patterns and identifying faulty nets within the circuit; c) providing an extraction algorithm; d) extracting a subset of the original circuit for failure diagnosis utilizing the provided extraction algorithm, wherein the extracted subset eliminates unnecessary circuit elements from the original circuit; e) generating test patterns for the extracted subset; f) mapping test patterns generated for the extracted subset back to the original circuit; g) testing the original circuit utilizing the test patterns generated for the extracted subset to diagnose reasons for failure of the identified faulty nets; h) generating a new set of interested nets from test results from the test utilizing the test patterns generated for the extracted subset; and i) repeating steps d through h until a smallest desired diagnostic resolution is reached.
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Specification