MICRO-PHASE ADJUSTING AND MICRO-PHASE ADJUSTING MIXER CIRCUITS DESIGNED WITH STANDARD FIELD EFFECT TRANSISTOR STRUCTURES
First Claim
1. A phase adjusting circuit comprising:
- an input node for receiving a first signal;
an output node;
a variable delay device comprising a plurality of field effect transistors comprising input diffusion regions adapted to be selectively biased, gates connected in series to said input node such that said first signal is propagated to said gates sequentially and output diffusions regions connected in parallel to said output node; and
a current source connected to said output node and adapted to bias said output node when all of said field effect transistors are off,wherein, when an input diffusion region of said selected field effect transistor is selectively biased and when an active edge of said first signal is propagated from said input node to a gate of said selected field effect transistor, a second signal is transmitted through a selected field effect transistor to said output node, andwherein a phase difference between said first signal and said second signal is based on delay in propagation of said first signal from said input node to said gate.
3 Assignments
0 Petitions
Accused Products
Abstract
Disclosed herein are embodiments of a programmable phase adjusting circuit, a programmable phase adjusting mixer circuit and design structures for these circuits. These circuits comprise a variable delay device connected between input and output nodes. The device includes multiple FETs with input diffusion regions that are connected to a voltage rail via switches so that they can be selectively biased, gates that are connected in series to the input node so that a periodic input signal can be propagated sequentially through each of the gates and output diffusion regions that are connected in parallel to the output node. A current source is connected between the output node and another voltage rail for biasing the output node when the variable delay device is off. The variable delay device enables a circuit in which small increments of selectable phase adjustments can be made to the periodic input signal as a function of propagation delay.
56 Citations
20 Claims
-
1. A phase adjusting circuit comprising:
-
an input node for receiving a first signal; an output node; a variable delay device comprising a plurality of field effect transistors comprising input diffusion regions adapted to be selectively biased, gates connected in series to said input node such that said first signal is propagated to said gates sequentially and output diffusions regions connected in parallel to said output node; and a current source connected to said output node and adapted to bias said output node when all of said field effect transistors are off, wherein, when an input diffusion region of said selected field effect transistor is selectively biased and when an active edge of said first signal is propagated from said input node to a gate of said selected field effect transistor, a second signal is transmitted through a selected field effect transistor to said output node, and wherein a phase difference between said first signal and said second signal is based on delay in propagation of said first signal from said input node to said gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
-
-
13. A phase adjusting mixer circuit comprising:
-
an input node for receiving a first signal; an output node; a variable delay device comprising a plurality of field effect transistors comprising input diffusion regions adapted to be selectively biased, gates connected in series to said input node such that said first signal is propagated to said gates sequentially and output diffusions regions connected in parallel to said output node, wherein, when an input diffusion region of said selected field effect transistor is selectively biased and when an active edge of said first signal is propagated from said input node to a gate of said selected field effect transistor, a second signal is transmitted through a selected field effect transistor to said output node, and wherein a phase difference between said first signal and said second signal is based on delay in propagation of said first signal from said input node to said gate; and a current source connected to said output node, wherein said current source is non-constant, independent of said first signal and is adapted to transmit a third signal to said output node, and wherein said output node is adapted to combine said second signal and said third signal. - View Dependent Claims (14, 15, 16)
-
-
17. A design structure embodied in a machine readable medium used in a design flow process, said design structure comprising a phase adjusting circuit comprising:
-
an input node for receiving a first signal; an output node; a variable delay device comprising a plurality of field effect transistors comprising input diffusion regions adapted to be selectively biased, gates connected in series to said input node such that said first signal is propagated to said gates sequentially and output diffusions regions connected in parallel to said output node; and a current source connected to said output node and adapted to bias said output node when all of said field effect transistors are off, wherein a second signal is transmitted through a selected field effect transistor to said output node when an input diffusion region of said selected field effect transistor is selectively biased and when an active edge of said first signal is propagated from said input node to a gate of said selected field effect transistor, and wherein a phase difference between said first signal and said second signal is based on delay in propagation of said first signal from said input node to said gate. - View Dependent Claims (18, 19, 20)
-
Specification