RESISTANCE CHANGE MEMORY AND WRITE METHOD OF THE SAME

• US 20090034320A1
• Filed: 07/31/2008
• Published: 02/05/2009
• Est. Priority Date: 08/02/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: UEDA, Yoshihiro
• Granted Patent: US 8,223,565 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2013/009 Write using potential difference applied between cell electrodes
• CPC Class Codes: G11C 2213/31 Material having complex metal oxide, e.g. perovskite structure
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/34 Material includes an oxide or a nitride
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

A resistance change memory includes a resistance change element having a high-resistance state and a low-resistance state in accordance with write information, and a write circuit configured to supply a write current that the write current flowing through the resistance change element is held constant before and after the resistance change element is changed from the high-resistance state to the low-resistance state, and apply a write voltage that the write voltage applied to the resistance change element is held constant before and after the resistance change element is changed from the low-resistance state to the high-resistance state.

Claims

1. A resistance change memory comprising:

a resistance change element having a high-resistance state and a low-resistance state in accordance with write information; and

a write circuit configured to supply a write current that the write current flowing through the resistance change element is held constant before and after the resistance change element is changed from the high-resistance state to the low-resistance state, and apply a write voltage that the write voltage applied to the resistance change element is held constant before and after the resistance change element is changed from the low-resistance state to the high-resistance state.

2. The memory according to claim 1, wherein the write circuit has a constant-current circuit configured to supply the write current, and a constant-voltage circuit configured to apply the write voltage.

3. The memory according to claim 2, which further comprises:

a first switch having one terminal connected to the constant-current circuit, and the other terminal connected to a first node;

a second switch having one terminal connected to a ground terminal, and the other terminal connected to the first node;

a third switch having one terminal connected to the constant-voltage circuit, and the other terminal connected to a second node; and

a fourth switch having one terminal connected to a ground terminal, and the other terminal connected to the second node, and

in which the first node is connected to one terminal of the resistance change element, and the second node is connected to the other terminal of the resistance change element,

when changing the resistance change element to the low-resistance state, the write current is supplied from the first switch to the fourth switch via the resistance change element by turning on the first switch and the fourth switch and turning off the second switch and the third switch, and

when changing the resistance change element to the high-resistance state, the write voltage is applied from the third switch to the second switch via the resistance change element by turning on the second switch and the third switch and turning off the first switch and the fourth switch.

4. The memory according to claim 2, which further comprises:

a first switch having one terminal connected to the constant-current circuit, and the other terminal connected to a node; and

a second switch having one terminal connected to the constant-voltage circuit, and the other terminal connected to the node, and

in which the node is connected to one terminal of the resistance change element,

when changing the resistance change element to the low-resistance state, the write current is supplied from the first switch to the resistance change element by turning on the first switch and turning off the second switch, and

when changing the resistance change element to the high-resistance state, the write voltage is applied from the second switch to the resistance change element by turning on the second switch and turning off the first switch.

5. The memory according to claim 1, which further comprises:

a cell transistor having a current path whose one end is connected to one terminal of the resistance change element;

a first wiring connected to the other terminal of the resistance change element; and

a second wiring connected to the other end of the current path of the cell transistor, and

in which a direction of the write current supplied when changing the resistance change element to the low-resistance state and a direction of the write voltage applied when changing the resistance change element to the high-resistance state are opposite to each other.

6. The memory according to claim 1, which further comprises:

a cell transistor having a current path whose one end is connected to one terminal of the resistance change element;

a first wiring connected to the other terminal of the resistance change element; and

a second wiring connected to the other end of the current path of the cell transistor, and having one end connected to a ground terminal, and

in which a direction of the write current supplied when changing the resistance change element to the low-resistance state and a direction of the write voltage applied when changing the resistance change element to the high-resistance state are the same.

7. The memory according to claim 1, which further comprises:

a diode having a current path whose one end is connected to one terminal of the resistance change element;

a first wiring connected to the other terminal of the resistance change element; and

a second wiring connected to the other end of the current path of the diode, and

in which a direction of the write current supplied when changing the resistance change element to the low-resistance state and a direction of the write voltage applied when changing the resistance change element to the high-resistance state are the same.

8. The memory according to claim 1, wherein the resistance change element is one of a magnetoresistive element, a chalcogenide element, and a transition metal oxide element.

9. The memory according to claim 1, which further comprises a cell transistor connected in series with the resistance change element, and

in which the cell transistor is operated in a saturation region when changing the resistance change element to the high-resistance state and the low-resistance state.

10. The memory according to claim 1, further comprising:

a cell transistor connected in series with the resistance change element; and

a driving circuit configured to set a gate voltage of the cell transistor at a first voltage when changing the resistance change element to the low-resistance state, and set the gate voltage of the cell transistor at a second voltage higher than the first voltage when changing the resistance change element to the high-resistance state.

11. A resistance change memory comprising a memory cell in which a resistance change element having a high-resistance state and a low-resistance state in accordance with write information and a cell transistor are connected in series, wherein

when changing the resistance change element from the high-resistance state to the low-resistance state, a write current is supplied from the resistance change element to the cell transistor, and

when changing the resistance change element from the low-resistance state to the high-resistance state, the write current is supplied from the cell transistor to the resistance change element.

12. The memory according to claim 11, further comprising a write circuit configured to supply an electric current that the write current flowing through the resistance change element is held constant before and after the resistance change element is changed to the low-resistance state, and apply a voltage that the write current flowing through the resistance change element is held constant before and after the resistance change element is changed to the high-resistance state.

13. The memory according to claim 12, wherein the write circuit has a constant-current circuit configured to supply the electric current, and a constant-voltage circuit configured to apply the voltage.

14. The memory according to claim 11, wherein the cell transistor is operated in a saturation region when changing the resistance change element to the high-resistance state and the low-resistance state.

15. The memory according to claim 11, further comprising a driving circuit configured to set a gate voltage of the cell transistor at a first voltage when changing the resistance change element to the low-resistance state, and set the gate voltage of the cell transistor at a second voltage higher than the first voltage when changing the resistance change element to the high-resistance state.

16. A write method of a resistance change memory including a resistance change element having a high-resistance state and a low-resistance state in accordance with write information,

the method comprising supplying a write current that the write current flowing through the resistance change element is held constant before and after the resistance change element is changed from the high-resistance state to the low-resistance state, and applying a write voltage that the write voltage applied to the resistance change element is held constant before and after the resistance change element is changed from the low-resistance state to the high-resistance state.

17. The method according to claim 16, wherein a direction of the write current supplied when changing the resistance change element to the low-resistance state and a direction of the write voltage applied when changing the resistance change element to the high-resistance state are opposite to each other.

18. The method according to claim 16, wherein a direction of the write current supplied when changing the resistance change element to the low-resistance state and a direction of the write voltage applied when changing the resistance change element to the high-resistance state are the same.

19. The method according to claim 16, in which the resistance change memory further includes a cell transistor connected in series with the resistance change element, and

which further comprises setting a gate voltage of the cell transistor at a first voltage when changing the resistance change element to the low-resistance state, and setting the gate voltage of the cell transistor at a second voltage higher than the first voltage when changing the resistance change element to the high-resistance state.

20. The method according to claim 16, wherein the resistance change element is one of a magnetoresistive element, a chalcogenide element, and a transition metal oxide element.