NAND MEMORY DEVICE COLUMN CHARGING

• US 20090034331A1
• Filed: 10/06/2008
• Published: 02/05/2009
• Est. Priority Date: 03/01/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Granted Patent: US 7,782,677 B2
• Time in Patent Office: Days
• US Class Current: 365/185.30
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on adjacent columns of an array. Maintaining the columns in a charged state prior to array operations (read, write, and program) reduces current surges and improves data read timing. Devices and methods charge the array columns at pre-charge and following array access operations.

Claims

1. A flash memory device comprising:

an array of memory cells having a column format arrangement, wherein each column of cells is coupled to a bit line, the bit lines arranged to form a first page and a second page; and

circuitry to apply a voltage to the columns to reduce a column coupling capacitance.

2. The flash memory device of claim 1, wherein the circuitry is to apply a single voltage to the columns.

3. The flash memory device of claim 1, wherein the circuitry is to maintain a positive voltage level on all the bit lines prior to read, write, and program operations.

4. The flash memory device of claim 1, wherein the bit lines are arranged in an alternating pattern such that every other bit line is coupled together to form one of the first page or the second page.

5. The flash memory device of claim 1, wherein the bit lines associated with the first page and the bit lines associated with the second page are to receive from the circuitry substantially identical voltages.

6. A method of improving data read timing comprising:

pre-charging all bit lines of a first page and a second page of a flash memory to a specified positive voltage level, the bit lines formed in a staggered arrangement; and

performing a logical operation on an active page while all column bit lines of the inactive page are maintained at the positive voltage level.

7. The method of claim 6, wherein performing includes performing a memory access operation.

8. The method of claim 7, wherein pre-charging includes re-charging all bit lines after performing a logical operation.

9. The method of claim 7, wherein pre-charging includes re-charging all bit lines before performing a next logical operation

10. The method of claim 7, wherein pre-charging includes pre-charging to reduce a current surge during the logical operation.

11. A flash device comprising:

a plurality memory cells arranged in columns along bit lines, the bit lines are coupled to form logical pages; and

a charging device to provide a positive voltage level to the bit lines prior to initiating a memory access operation to reduce a transient current output from the charging device.

12. The flash device of claim 11, wherein the charging device is to further provide the positive voltage level to improve data read timing.

13. The flash device of claim 11, wherein the positive voltage to the bit lines is to reduce an effective column coupling capacitance.

14. The flash device of claim 11, wherein the logical pages are interwoven using an alternating bit line arrangement.

15. The flash device of claim 14, wherein the logical pages include an active page and an inactive page, and wherein positive voltage to the bit lines associated with the inactive page is maintained during the memory access operation.

16. The flash device of claim 11, wherein the charging device is coupled to a memory controller.

17. The flash device of claim 11, wherein the charging device is to provide the positive voltage level when the memory cells receive power.

18. The flash device of claim 11, wherein the bit lines receive the positive voltage level at power-up, read execution and verify operations.

19. The flash device of claim 11, wherein the bit lines are coupled to receive logical information provided to one or more word lines during the memory access operation.

20. The flash device of claim 11, wherein the circuitry is to charge the bit lines to about one volt.

21. The flash device of claim 11, wherein at least one of the cells of the array of memory cells is to store a multiple data bits.

22. The flash device of claim 11, wherein cells in the array are to store multiple voltage levels.