METHOD, APPARATUS, AND SYSTEM FOR IMPROVED READ OPERATION IN MEMORY

• US 20090034337A1
• Filed: 08/01/2007
• Published: 02/05/2009
• Est. Priority Date: 08/01/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi
• Granted Patent: US 7,898,863 B2
• Time in Patent Office: Days
• US Class Current: 365/185.180
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

Various embodiments include methods, apparatus, and systems for reading an adjacent cell of a memory array in an electronic device to determine a threshold voltage value of the adjacent cell, the adjacent cell being adjacent a target cell, and reading the target cell of the memory array using a wordline voltage value based on the threshold voltage value of the adjacent cell. Additional apparatus, systems, and methods are disclosed.

Claims

1. A method, comprising:

determining a threshold voltage value of an adjacent cell of a memory array, the adjacent cell being adjacent a target cell of the memory array; and

reading the target cell of the memory array using a voltage value on a line used to access the target cell, wherein the voltage value is based on the threshold voltage value of the adjacent cell.

2. The method of claim 1, wherein the target cell is located in a first row of the memory array, wherein the adjacent cell is located in a second row of the memory array, and wherein the first row is adjacent the second row.

3. The method of claim 1, wherein the target cell and the adjacent cell are located in a row of the memory array.

4. The method of claim 1, comprising:

receiving a first command to read the target cell; and

reading the adjacent cell without receiving a second command to read the adjacent cell.

5. The method of claim 1, comprising:

determining a shift threshold voltage value of the target cell corresponding to a shift in the threshold voltage value of the adjacent cell.

6. The method of claim 5, wherein determining the shift threshold voltage value comprises:

accessing a storage area to locate an entry indicating the shift threshold voltage value based on the threshold voltage value of the adjacent cell.

7. The method of claim 6, wherein reading the adjacent cell comprises applying an additional voltage having a first initial voltage value to a line used to access the adjacent cell, and wherein the voltage on the line used to access the target cell has a second initial voltage value approximately equal to a sum of the first initial voltage value and the shift threshold voltage value.

8. A method, comprising:

reading an adjacent cell of a memory array to obtain feedback information, the adjacent cell being adjacent a target cell; and

reading the target cell of the memory array based on the feedback information.

9. The method of claim 8, wherein the feedback information is obtained by determining a shift threshold voltage value of the target cell based on a threshold voltage value of the adjacent cell.

10. The method of claim 9, wherein determining the shift threshold voltage value comprises:

calculating the shift threshold voltage value based on the threshold voltage value of the adjacent cell.

11. The method of claim 10, wherein the calculating assumes a substantially linear relationship between the shift threshold voltage value and the threshold voltage value of the adjacent cell.

12. The method of claim 9, wherein reading the adjacent cell comprises:

applying a voltage with a first voltage value to a line used to access the adjacent cell to determine the threshold voltage value of the adjacent cell; and

changing the first voltage value to a second voltage value when the threshold voltage value of the adjacent cell is unsuccessfully determined.

13. The method of claim 12, wherein reading the target cell comprises:

applying an additional voltage to a line used to access the target cell, wherein the additional voltage has a voltage value approximately equal to a sum of the shift threshold voltage value and the first voltage value.

14. The method of claim 13, wherein the threshold voltage value of the adjacent cell is represented by a logical value having at least two data bits.

15. A method, comprising:

receiving a command to read a target cell of a memory array;

reading cells adjacent the target cell before reading the target cell;

obtaining feedback information from reading the cells adjacent the target cell; and

reading the target cell using a voltage value determined at least in part by the feedback information.

16. The method of claim 15, wherein obtaining the feedback information comprises determining shift threshold voltage values of the target cell based on threshold voltage values of the cells in the second row, and wherein each of the shift threshold voltage values is determined based on one of the threshold voltage values.

17. The method of claim 16, wherein reading the target cell comprises:

applying a voltage to a line used to access the target cell, wherein a first value of the voltage is a function of the shift threshold voltage values and an initial value of an additional voltage used to read the cells of the second row.

18. The method of claim 17, wherein the first value is approximately equal to a sum of the shift threshold voltage values and the initial value.

19. The method of claim 18, comprising:

changing the first value to a second value between reading a first logical page associated with the target cell and reading a second logical page associated with the target cell.

20. The method of claim 18, wherein the initial value is approximately equal to a ground potential.

21. The method of claim 15, wherein reading the cells in the second row comprises:

reading a first cell, reading a second cell, and reading a third cell, wherein the first cell is located adjacent the target cell in a bit line direction, wherein the second cell is located diagonally adjacent the target cell in a first diagonal direction, and wherein the third cell is located diagonally adjacent the target cell in a second diagonal direction different from the first diagonal direction.

22. The method of claim 15, wherein reading the target cell comprises:

determining a threshold voltage value of the target cell, wherein the threshold voltage value of the target cell is represented as a logical value having at least two data bits.

23. A method comprising:

reading a first group of adjacent cells of a memory array, the first group of adjacent cells being adjacent a first target cell;

obtaining first feedback information from reading the first group of adjacent cells;

reading a second group of adjacent cells of the memory array, the second group of adjacent cells being adjacent a second target cell;

obtaining second feedback information from reading the second group of cells;

reading the first target cell of the memory array using a voltage with a first voltage value based on the first feedback information; and

reading the second target cell of the memory array using the voltage with a second voltage value based on the second feedback information.

24. The method of claim 23, wherein obtaining the first feedback information comprises determining a first voltage shift of a threshold voltage of the first target cell based on a threshold voltage of each cell in the first group of adjacent cells, and wherein obtaining the second feedback information comprises determining a second voltage shift of a threshold voltage of the second target cell based on a threshold voltage of each cell in the second group of adjacent cells.

25. The method of claim 24, wherein the first and second target cells are located in a row of the memory array, and wherein reading the first and second target cells comprises:

applying to the line used to access the first and the second target cells the voltage with an initial voltage value lower than the first voltage value;

increasing the voltage;

reading the first target cell when the voltage reaches the first voltage value; and

reading the second target cell when the voltage reaches a second voltage value greater than the first voltage value.

26. The method of claim 25 comprising:

counting a number of signal cycles of a count signal, wherein the first target cell is read when the number reaches a first quantity, and wherein the second target cell is read when the number reaches a second quantity.

27. A method comprising:

receiving from an electronic device a program command to read a target cell of a memory array;

reading the first cell to determine a first threshold voltage value of the first cell; and

reading the target cell using a voltage with a voltage value based on the first threshold voltage value.

28. The method of claim 27, wherein reading the target cell comprises:

applying the voltage to a line used to access the target cell, wherein reading the first cell comprises applying an additional voltage to an additional line used to access the first cell, and wherein the voltage has a first initial voltage value greater than a second initial voltage value of the additional voltage.

29. The method of claim 27, wherein receiving the program command comprises:

transferring a signal associated with the program command via a conductive medium on a circuit board.

30. The method of claim 27, wherein receiving the program command comprises:

transferring a signal associated with the program command via a conductive medium, wherein the conductive medium is located inside a semiconductor package.

31. An apparatus comprising:

a memory array comprising a first cell and a second cell; and

a module coupled to the memory array, the module configured to read the first cell to determine a first threshold voltage value of the first cell, and configured to read the second cell using a voltage with voltage value based on the first threshold voltage value.

32. The apparatus of claim 31, wherein each of the first and second cells is configured to store a logical value having multiple data bits.

33. The apparatus of claim 31, wherein the circuit is configured to apply an additional voltage to the line used to access the first cell when reading the first cell, and to apply the voltage to an additional line used to access the second cell when reading the second cell, and wherein the voltage has an initial voltage value greater than an initial voltage value of the additional voltage.

34. The apparatus of claim 33 comprising:

a counter configured to count a number of signal cycles of a count signal, wherein the number is zero when the initial voltage value applied to the line is equal to the initial voltage value applied to the additional line.

35. The apparatus of claim 33, wherein the initial voltage value of the additional voltage is approximately equal to a ground voltage potential.

36. An apparatus comprising:

a memory array comprising cells; and

a module coupled to the memory array, the module configured to read a group of cells among the cells, configured to obtain feedback information from reading the group of cells, and configured to read a target cell among the cells based on the feedback information.

37. The apparatus of claim 36, wherein the feedback information comprises a sum of voltage shifts of a threshold voltage of the target cell, and wherein each of the voltage shifts is determined based on a threshold voltage of each cell of the group of cells.

38. The apparatus of claim 37, comprising:

a storage area configured to store entries, wherein each of the entries comprises an indication of each of the voltage shifts based on a threshold voltage of one cell of the group of cells.

39. The apparatus of claim 37 comprising:

a storage area configured to store programming codes to determine a voltage value of each of the voltage shifts based on a threshold voltage of one cell of the group of cells.

40. The apparatus of claim 36, comprising:

a counter configured to count a number of signal cycles of a count signal, wherein the circuit is configured to read the second cell when the number reaches a selected quantity.

41. The apparatus of claim 36, wherein the target cell is located in a first row of the memory array, wherein the group of cells comprises a first cell, a second cell, and a third cell located in a second row of the memory array, wherein the first cell is located adjacent the target cell in a bit line direction, wherein the second cell is located diagonally adjacent the target cell in a first diagonal direction, and wherein the third cell is located diagonally adjacent the target cell in a second diagonal direction different from the first diagonal direction.

42. The apparatus of claim 41, wherein the group of cells comprise a fourth cell and a fifth cell, wherein the fourth and the fifth cells are located in the first row, wherein the fourth cell is located adjacent a first side of the target cell, and wherein the fifth cell is located adjacent a second side of the target cell.

43. The apparatus of claim 41, comprising:

a wordline coupled to the target cell; and

an additional wordline coupled to each cell of the group of cells, wherein the module is to apply the voltage to the wordline to read the target cell, and to apply an additional voltage to the additional wordline to read the group of cells, and wherein the voltage has an initial voltage value greater than an initial voltage value of the additional voltage.

44. A system comprising:

a flash memory device comprising a memory array including a first cell and a second cell, and a module coupled to the memory array, the module configured to read the first cell to determine a first threshold voltage of the first cell, and configured to read the second cell using a voltage with a voltage value based on a voltage value of the first threshold voltage; and

a processor configured to provide a program command to the flash memory device to read the second cell, and to process information from reading the second cell to produce processed information.

45. The system of claim 44, wherein the circuit is configured to read the first cell without receiving from the processor a read command to read the first cell.

46. The system of claim 44 comprising:

a pixel array coupled to the flash memory device.

47. The system of claim 44 comprising:

a transceiver coupled to the flash memory device and configured to perform at least one of transferring information from at least one of the processor and the flash memory device to an antenna coupled to the transceiver and transferring information received at the antenna to at least one of the processor and the flash memory device.