Eight Transistor SRAM Cell with Improved Stability Requiring Only One Word Line

• US 20090034345A1
• Filed: 08/01/2007
• Published: 02/05/2009
• Est. Priority Date: 01/18/2006
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chan, Yuen H., Plass, Donald W., Huott, William V.
• Granted Patent: US 7,606,060 B2
• Time in Patent Office: Days
• US Class Current: 365/189.140
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell.

Claims

1-17. -17. (canceled)

18. A static random access memory comprising in combination:

a plurality of bi-stable memory cells arranged in rows and columns;

a pair of write bit lines common to each memory cell in a column;

a single pre-charged read bit line common to each memory cell in a column;

a pair of field effect transistors respectively connecting each cell in column to said pair of write bit lines, a gate of each of said pair connected respectively to said pair of write bit lines for writing data into each cell;

a single field effect transistor respectively connecting each cell in a column to said read bit line, with its gate coupled respectively to a node of each memory cell in a column for reading data from said cell;

a single field effect transistor whose gate is coupled to a word line to control both read access and write access to each cell in a row.

19. A static random access memory comprising in combination:

a plurality of bi-stable memory cells arranged in rows and columns;

a pair of write bit lines common to each memory cell in a column;

a single pre-charge read bit line common to each memory cell in a column;

a pair of n-type field effect transistors respectively connecting each cell in a column to said pair of write bit lines, each of said pair comprised of a source, a drain and a gate, with the gate of each of said pair connected respectively to said pair of write bit lines for writing data into each cell;

a single n-type field effect transistor respectively connecting each cell in a column to said read bit line, said single n-type field effect transistor comprised of a source, a drain, and a gate, with the gate coupled respectively to a node of each memory cell in a column for reading data from said cell;

a single n-type field effect transistor whose gate is coupled to a word line to control both read access and write access to each cell in a row.