PROCESS OF SEMICONDUCTOR FABRICATION WITH MASK OVERLAY ON PITCH MULTIPLIED FEATURES AND ASSOCIATED STRUCTURES

• US 20090035665A1
• Filed: 07/31/2007
• Published: 02/05/2009
• Est. Priority Date: 07/31/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tran, Luan C.
• Granted Patent: US 8,563,229 B2
• Time in Patent Office: Days
• US Class Current: 430/5
• CPC Class Codes: H01L 21/0274 Photolithographic processes
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

Abstract

Spacers are formed by pitch multiplication and a layer of negative photoresist is deposited on and over the spacers to form additional mask features. The deposited negative photoresist layer is patterned, thereby removing photoresist from between the spacers in some areas. During patterning, it is not necessary to direct light to the areas where negative photoresist removal is desired, and the clean removal of the negative photoresist from between the spacers is facilitated. The pattern defined by the spacers and the patterned negative photoresist is transferred to one or more underlying masking layers before being transferred to a substrate.

Claims

1. A method for patterning a substrate, comprising:

providing a photoresist layer over an amorphous carbon layer;

patterning the photoresist layer to form photoresist features;

blanket depositing a layer of spacer material over the photoresist features;

preferentially etching the spacer material from horizontal surfaces to define spacers on sidewalls of the photoresist features;

preferentially removing the photoresist features relative to the spacers;

transferring a pattern defined by the spacers to the amorphous carbon layer to define amorphous carbon mask features;

depositing negative photoresist over and around the amorphous carbon mask features;

patterning the negative photoresist to form a mask pattern defined by the amorphous carbon mask features and the negative resist; and

transferring the mask pattern to a substrate.

2. The method of claim 1, further comprising trimming the photoresist features before blanket depositing the layer of spacer material.

3. The method of claim 2, wherein trimming the photoresist features comprises exposing the photoresist features to an isotropic etch.

4. The method of claim 1, further comprising removing the spacers before depositing the negative photoresist.

5. The method of claim 1, wherein blanket depositing the layer of spacer material comprises depositing the spacer material by atomic layer deposition.

6. The method of claim 1, wherein the spacer material is silicon oxide.

7. The method of claim 1, further comprising transferring the pattern defined by the spacers to a hardmask layer before transferring the pattern defined by the spacers to the amorphous carbon layer.

8. The method of claim 7, wherein providing the photoresist layer over the amorphous carbon layer comprises providing the photoresist layer directly on the hardmask layer.

9. The method of claim 7, wherein the hardmask layer comprises an antireflective coating.

10. The method of claim 1, wherein the amorphous carbon is transparent carbon.

11. The method of claim 1, wherein transferring the mask pattern to the substrate defines interconnect lines.

12. The method of claim 1, wherein transferring the mask pattern to the substrate defines control gates of a memory device.

13. The method of claim 1, wherein the spacers extend in spaced, generally parallel relation to one another for at least a part of a length of the spacers.

14. A method for semiconductor fabrication, comprising:

providing features spaced apart by about 50 nm or less;

depositing negative photoresist between and above the features; and

patterning the negative photoresist using a photolithographic technique to selectively remove at least some of the negative photoresist from between at least some sections of the features, wherein the features have a feature pitch below a minimum pitch of the photolithographic technique.

15. The method of claim 14, wherein selectively removing comprises selectively exposing the negative photoresist to light, wherein an intensity of the light is about 20 mJ/cm or more.

16. The method of claim 14, wherein the feature pitch is about 100 nm or less.

17. The method of claim 14, wherein providing features comprises:

providing a plurality of mandrels;

depositing a layer of material on sidewalls and top surfaces of the mandrels;

anisotropically etching the layer of material to form the mask features on sidewalls of the mandrels; and

preferentially removing the mandrels relative to the mask features.

18. The method of claim 17, wherein providing the plurality of mandrels comprises patterning a photoresist layer, wherein the mandrels are formed of photoresist.

19. A method for forming a mask for patterning a substrate, comprising:

patterning a photoresist layer to define photoresist mask features;

deriving other mask features from the photoresist mask features without performing photolithography, the other mask features having a pitch less than about half a pitch of the photoresist mask features;

depositing negative photoresist over and above the other mask features;

patterning the negative photoresist to expose at least some portions of the other mask features; and

transferring a pattern defined by the other mask features and the patterned negative photoresist to an underlying substrate.

20. The method of claim 19, wherein selectively removing the photoresist mask features comprises performing a development process without exposing the photoresist mask features to light through a reticle.

21. The method of claim 19, wherein patterning the photoresist layer comprises performing photolithography, wherein the pitch of the other mask features is less than a minimum pitch of the photolithographic technique used to define the photoresist mask features.

22. The method of claim 21, wherein performing photolithography comprises exposing photoresist to light having a wavelength chosen from the group consisting of 13.7 nm, 157 nm, 193 nm, 248 nm or 365 nm wavelength light.

23. The method of claim 19, wherein deriving other mask features comprises:

blanket depositing a layer of spacer material on the photoresist mask features;

exposing the layer of spacer material to a directional etch to form spacers on sidewalls of the photoresist mask features, wherein the spacers constitute the other mask features; and

selectively removing the photoresist mask features.

24. The method of claim 19, wherein the substrate is a partially fabricated integrated circuit, wherein patterning the negative photoresist comprises exposing the portions of the other mask features directly overlying an array region of the partially fabricated integrated circuit.

25. The method of claim 24, wherein patterning the negative photoresist comprises defining peripheral mask features directly over a periphery region of the partially fabricated integrated circuit.

26. A partially formed integrated circuit, comprising:

a substrate;

a primary mask layer overlying the substrate, the primary mask layer formed of a material different from photoresist;

a hard mask layer overlying the primary mask layer;

mask features overlying the hard mask layer; and

patterned negative photoresist on a same level as the mask features, at least some of the negative photoresist extending above an uppermost part of the mask features.

27. The partially formed integrated circuit of claim 26, wherein the primary mask layer is amorphous carbon.

28. The partially formed integrated circuit of claim 26, wherein the hard mask layer is an anti-reflective coating.

29. The partially formed integrated circuit of claim 26, wherein the mask features are spacers.

30. The partially formed integrated circuit of claim 29, wherein the spacers are formed of silicon oxide.

31. The partially formed integrated circuit of claim 26, wherein the substrate comprises a plurality of layers of different materials.

32. The partially formed integrated circuit of claim 31, wherein the partially formed integrated circuit is a memory device.

33. The partially formed integrated circuit of claim 26, wherein the mask features correspond to features of a gate array.

34. The partially formed integrated circuit of claim 26, wherein the mask features correspond to features of a logic array.

35. The partially formed integrated circuit of claim 26, wherein the mask features have a pitch of about 50 nm or less.

36. The partially formed integrated circuit of claim 26, wherein the pitch is about 30 nm or less.