Method of Forming High Density Trench FET with Integrated Schottky Diode
First Claim
1. A method of forming a monolithically integrated trench FET and Schottky diode, the method comprising:
- forming a pair of trenches extending through an upper silicon layer and terminating within a lower silicon layer, the upper and lower silicon layers having a first conductivity type, the upper silicon layer extending over the lower silicon layer;
forming first and second silicon regions of a second conductivity type in the upper silicon layer between the pair of trenches;
forming a third silicon region of the first conductivity type extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer;
performing a silicon etch to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain, the outer portions of the first silicon region forming source regions; and
forming an interconnect layer filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer, the interconnect layer forming a Schottky contact with the portion of the upper silicon.
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Abstract
A method of forming a monolithically integrated trench FET and Schottky diode includes the following steps. Two trenches are formed extending through an upper silicon layer and terminating within a lower silicon layer. The upper and lower silicon layers have a first conductivity type. First and second silicon regions of a second conductivity type are formed in the upper silicon layer between the pair of trenches. A third silicon region of the first conductivity type is formed extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer. A silicon etch is performed to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain, the outer portions forming source regions. An interconnect layer is formed filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer. The interconnect layer electrically contacts the second silicon region so as to form a Schottky contact therebetween.
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Citations
19 Claims
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1. A method of forming a monolithically integrated trench FET and Schottky diode, the method comprising:
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forming a pair of trenches extending through an upper silicon layer and terminating within a lower silicon layer, the upper and lower silicon layers having a first conductivity type, the upper silicon layer extending over the lower silicon layer; forming first and second silicon regions of a second conductivity type in the upper silicon layer between the pair of trenches; forming a third silicon region of the first conductivity type extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer; performing a silicon etch to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain, the outer portions of the first silicon region forming source regions; and forming an interconnect layer filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer, the interconnect layer forming a Schottky contact with the portion of the upper silicon. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of forming a monolithically integrated trench MOSFET and Schottky diode, the method comprising:
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using a mask, forming a first plurality of trenches extending into and terminating in an upper silicon layer, the upper silicon layer extending over a lower silicon layer, the upper and lower silicon layers having a first conductivity type; filling the first plurality of trenches with silicon material of a second conductivity type; performing a thermal cycle to diffuse out the silicon material into the upper silicon layer and under the mask; using the mask, forming a second plurality of trenches extending through the silicon material, the upper silicon layer, and terminating within the lower silicon layer such that the diffused out portions of the silicon material under the mask remain on each side of corresponding trenches; forming a first silicon region of the first conductivity type extending into the diffused out portions such that remaining lower portions of the diffused out portions between every two adjacent trenches form two body regions separated by a portion of the upper silicon layer; performing a silicon etch to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain, the outer portions of the first silicon region forming source regions; and forming an interconnect layer filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer, the interconnect layer forming a Schottky contact with the portion of the upper silicon.
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16. A method of forming a monolithically integrated trench MOSFET and Schottky diode, the method comprising:
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using a mask, forming a plurality of trenches extending through an upper silicon layer and terminating within a lower silicon layer, the upper and lower silicon layers having a first conductivity type, the upper silicon layer extending over the lower silicon layer; performing a two-pass angled implant to form first silicon regions of a second conductivity type in the upper silicon layer along upper sidewalls of each trench; forming a second silicon region of the first conductivity type extending into the first silicon regions between every two adjacent trench such that remaining lower portions of the first silicon regions form two body regions between every two adjacent trenches, the two body regions being separated by a portion of the upper silicon layer; performing a silicon etch to form a contact opening extending through the second silicon region such that outer portions of the second silicon region remain between every two adjacent trenches, the outer portions of the second silicon region forming source regions; and forming an interconnect layer filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer, the interconnect layer forming a Schottky contact with the portion of the upper silicon. - View Dependent Claims (17)
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18. A method of forming a monolithically integrated trench MOSFET and Schottky diode, the method comprising:
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using a mask, forming a first plurality of trenches extending into and terminating at a first depth within an upper silicon layer, the upper silicon layer extending over a lower silicon layer, the upper and lower silicon layers having a first conductivity type; performing a two-pass angled implant to form first silicon regions of a second conductivity type in the upper silicon layer along sidewalls of each trench; using the mask, extending the plurality of trenches deeper to a second depth with the lower silicon layer; forming a second silicon region of the first conductivity type extending into the first silicon regions between every two adjacent trench such that remaining lower portions of the first silicon regions form two body regions between every two adjacent trenches, the two body regions being separated by a portion of the upper silicon layer; performing a silicon etch to form a contact opening extending through the second silicon region such that outer portions of the second silicon region remain between every two adjacent trenches, the outer portions of the second silicon region forming source regions; and forming an interconnect layer filling the contact opening so as to electrically contact the source regions and the portion of the upper silicon layer, the interconnect layer forming a Schottky contact with the portion of the upper silicon. - View Dependent Claims (19)
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Specification