METHOD OF FORMING DIELECTRIC LAYERS ON A SUBSTRATE AND APPARATUS THEREFOR

• US 20090035927A1
• Filed: 07/30/2007
• Published: 02/05/2009
• Est. Priority Date: 07/30/2007
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: GOYANI, TEJAL, OLSEN, CHRISTOPHER S., SWENBERG, JOHANES
• Granted Patent: US 7,910,497 B2
• Time in Patent Office: Days
• US Class Current: 438/585
• CPC Class Codes: C23C 16/0272 Deposition of sub-layers, e.g. to promote the adhesion of the main coating
• CPC Class Codes: C23C 16/345 Silicon nitride
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/3141 Deposition using atomic layer deposition techniques [ALD]
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

Methods of forming dielectric layers on a substrate comprising silicon and oxygen are disclosed herein. In some embodiments, a method of forming a dielectric layer on a substrate includes provide a substrate having an exposed silicon oxide layer; treating an upper surface of the silicon oxide layer with a plasma; and depositing a silicon nitride layer on the treated silicon oxide layer via atomic layer deposition. The silicon nitride layer may be exposed to a plasma nitridation process. The silicon oxide and silicon nitride layers may be subsequently thermally annealed. The dielectric layers may be used as part of a gate structure.

Claims

1. A method of forming a dielectric layer on a substrate, comprising:

providing a substrate having an exposed silicon oxide layer;

treating an upper surface of the silicon oxide layer with a plasma; and

depositing a silicon nitride layer on the treated silicon oxide layer via atomic layer deposition at a temperature from about 300 degrees Celsius to about 700 degrees Celsius.

2. The method of claim 1, wherein providing a substrate having an exposed silicon oxide layer comprises:

forming a silicon oxide layer on the substrate by annealing the substrate in an oxidizing atmosphere.

3. The method of claim 2, further comprising:

removing a native oxide from the substrate before forming the silicon oxide layer.

4. The method of claim 1, wherein treating an upper surface of the silicon oxide layer with a plasma comprises:

exposing the upper surface of the silicon oxide layer to a plasma comprising nitrogen.

5. The method of claim 4, wherein the plasma further comprises an inert gas.

6. The method of claim 1, wherein treating an upper surface of the silicon oxide layer with a plasma comprises:

exposing the upper surface of the silicon oxide layer to a plasma comprising an inert gas.

7. The method of claim 1, wherein treating an upper surface of the silicon oxide layer with a plasma comprises:

exposing the upper surface of the silicon oxide layer to a plasma formed by a power supply operating in a pulsed wave mode and having a duty cycle as low as about 5 percent.

8. The method of claim 7, wherein the power supply provides power at a pulse frequency of about 10 kHz.

9. The method of claim 1, wherein the silicon nitride layer is deposited to a thickness of less than about 80 Å

.

10. The method of claim 1, wherein the silicon nitride layer is deposited to a thickness of less than about 20 Å

.

11. The method of claim 1, further comprising:

exposing the silicon nitride layer to a plasma.

12. The method of claim 11, wherein the plasma comprises nitrogen.

13. The method of claim 11, wherein the plasma comprises an inert gas.

14. The method of claim 11, further comprising:

annealing the silicon oxide and silicon nitride layers.

15. The method of claim 1, further comprising:

annealing the silicon oxide and silicon nitride layers.

16. A method of forming a dielectric layer on a substrate, comprising:

providing a substrate comprising silicon;

forming a silicon oxide layer on the substrate by annealing the substrate in an oxidizing atmosphere;

treating an upper surface of the silicon oxide layer with a plasma;

depositing a silicon nitride layer on the treated silicon oxide layer via atomic layer deposition at a temperature from about 300 degrees Celsius to about 700 degrees Celsius;

exposing the silicon nitride layer to a plasma; and

annealing the silicon oxide and silicon nitride layers.

17. A method of forming a gate structure on a substrate, comprising:

providing substrate having an exposed silicon oxide layer

treating an upper surface of the silicon oxide layer with a plasma;

depositing a silicon nitride layer on the silicon oxide layer via atomic layer deposition at a temperature from about 300 degrees Celsius to about 700 degrees Celsius; and

forming a gate electrode layer above the silicon nitride layer.

18. The method of claim 17, wherein providing a substrate having an exposed silicon oxide layer comprises:

forming a silicon oxide layer on the substrate by annealing the substrate in an oxidizing atmosphere.

19. The method of claim 17, wherein treating an upper surface of the silicon oxide layer with a plasma comprises:

exposing the upper surface of the silicon oxide layer to a plasma comprising at least one of nitrogen (N₂), ammonia (NH₃), argon (Ar), helium (He), krypton (Kr), neon (Ne), or xenon (Xe).

20. The method of claim 17, further comprising:

exposing the silicon nitride layer to a plasma comprising at least one of nitrogen (N₂), ammonia (NH₃), argon (Ar), helium (He), krypton (Kr), neon (Ne), or xenon (Xe).

21. The method of claim 17, further comprising:

annealing the silicon oxide and silicon nitride layers.

22. The method of claim 17, further comprising:

forming a layer disposed between the silicon nitride layer and the gate electrode layer, the layer comprising at least two of silicon, oxygen, or aluminum.

23. The method of claim 17, wherein the gate electrode layer comprises polysilicon or tantalum.

24-28. -28. (canceled)

29. A method of forming a dielectric layer on a substrate, comprising:

providing a substrate having an exposed silicon oxide layer;

treating an upper surface of the silicon oxide layer with a plasma, wherein treating an upper surface of the silicon oxide layer with a plasma comprises exposing the upper surface of the silicon oxide layer to a plasma formed by a power supply operating in a pulsed wave mode and having a duty cycle as low as about 5 percent; and

depositing a silicon nitride layer on the treated silicon oxide layer via atomic layer deposition.

30. The method of claim 29, wherein the power supply provides power at a pulse frequency of about 10 kHz.

31. The method of claim 29, wherein the silicon nitride layer is deposited to a thickness of less than about 80 Å

.