METHOD AND CONFIGURATION FOR CONNECTING TEST STRUCTURES OR LINE ARRAYS FOR MONITORING INTEGRATED CIRCUIT MANUFACTURING
First Claim
1. A test chip, comprising:
- at least one level having an m×
n array of regions, where m and n are integers, each region capable of including at least one test structure, at least some of the regions including respective test structures,the level having m+1 driver lines oriented in a first direction, the m+1 driver lines connected to collectively provide input signals to all of the test structures,the level having 4n receiver lines arranged in a second direction, the 4n receiver lines connected to collectively receive output signals from all of the test structures,wherein the test structures are arranged and connected so that each of the structures can be individually addressed for testing using the m+1 driver lines and 4n receiver lines.
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Abstract
A test chip comprises at least one level having an array of regions. Each region is capable of including at least one test structure. At least some of the regions include respective test structures. The level has a plurality of driver lines that provide input signals to the test structures. The level has a plurality of receiver lines that receive output signals from the test structures. The level has a plurality of devices for controlling current flow. Each test structure is connected to at least one of the driver lines with a first one of the devices in between. Each test structure is connected to at least one of the receiver lines with a second one of the devices in between, so that each of the test structures can be individually addressed for testing using the driver lines and receiver lines.
89 Citations
42 Claims
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1. A test chip, comprising:
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at least one level having an m×
n array of regions, where m and n are integers, each region capable of including at least one test structure, at least some of the regions including respective test structures,the level having m+1 driver lines oriented in a first direction, the m+1 driver lines connected to collectively provide input signals to all of the test structures, the level having 4n receiver lines arranged in a second direction, the 4n receiver lines connected to collectively receive output signals from all of the test structures, wherein the test structures are arranged and connected so that each of the structures can be individually addressed for testing using the m+1 driver lines and 4n receiver lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 39)
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8. A test chip, comprising:
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at least one level having an array of regions, each region capable of including at least one test structure, at least some of the regions including respective test structures, the level having a plurality of driver lines that provide input signals to the test structures, the level having a plurality of receiver lines that receive output signals from the test structures, the level having a plurality of devices for controlling current flow, wherein each test structure is connected to at least one of the driver lines with a first one of the devices therebetween, and each test structure is connected to at least one of the receiver lines with a second one of the devices therebetween, so that each of the test structures can be individually addressed for testing using the driver lines and receiver lines. - View Dependent Claims (9, 10, 11, 12, 40)
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13. A test chip, comprising:
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at least one level having an array of regions with m columns and n rows, where m and n are integers, each region capable of including at least one test structure, at least some of the regions including respective test structures, the level having m+1 driver lines oriented in a first direction, with the m columns arranged between successive ones of the m+1 driver lines, each test structure having two inputs connected by respective diodes, transistors, or controlled switches to a respective two of the driver lines, the m+1 driver lines collectively providing input signals to all of the test structures, the level having 4n receiver lines oriented in a second direction, each of the n rows arranged between a respective first pair of the 4n receiver lines on a first side thereof and a respective second pair of the 4n receiver lines on a second side thereof, each test structure having first and second outputs connected by respective diodes, transistors or controlled switches to respective ones of the receiver lines on the first and second side of that test structure, so that the 4n receiver lines collectively receive output signals from all of the test structures, whereby each of the structures can be individually addressed for testing. - View Dependent Claims (14, 15, 41)
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16. A test chip, comprising:
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at least one layer having n regions, where n an integer, each region capable of including at least one test structure, at least some of the regions including respective test structures, each comprising a nest of m parallel lines, where m is an integer, the at least one layer having m driver lines, the m driver lines connected to provide input signals to the respective m parallel lines in each nest, the at least one layer having at least 2n receiver lines, the at least 2n receiver lines connected to collectively receive output signals from all of the test structures, wherein the test structures are arranged and connected to the m driver lines and at least 2n receiver lines so that a presence of a short or open circuit defect in any of the nests can be identified. - View Dependent Claims (17, 18, 19, 20, 21, 22, 42)
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23. A test method, comprising the steps of:
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(a) forming circuit paths for at least one level of a chip, the level having an m×
n array of regions, where m and n are integers, at least some of the regions including respective test structures,(b) forming m+1 driver lines oriented in a first direction, each test structure being connected to at least one of the driver lines; (c) forming 4n receiver lines arranged in a second direction, each test structure being connected to at least one of the receiver lines; (d) individually addressing all the test structures using the m+1 driver lines and 4n receiver lines; and (e) providing input signals to all of the test structures using the m+1 driver lines, and (f) receiving output signals from all of the test structures using the 4n receiver lines. - View Dependent Claims (24, 25, 26, 27, 28)
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29. A test method, comprising the steps of:
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(a) forming circuit paths for at least one layer having n regions, where n is an integer, each region capable of including at least one test structure, at least some of the regions including respective test structures, each comprising a nest of m parallel lines, where m is an integer, (b) forming m driver lines for the at least one layer; (c) forming at least 2n receiver lines for the at least one layer; (d) providing input signals to the respective m parallel lines in each nest using the m driver lines; (e) measuring output signals from all of the test structures using the at least 2n receiver lines; and (f) identifying the presence of a short or open circuit defect in any of the nests based on the output signals received by way of the at least 2n receiver lines. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36, 37)
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38. A test chip, comprising:
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at least one layer having a vector of regions, each region capable of including at least one test structure, at least some of the regions including respective test structures, the layer having a plurality of driver lines that provide input signals to the test structures, the layer having a plurality of receiver lines that receive output signals from the test structures, the layer having a plurality of devices for controlling current flow, wherein each test structure is connected to at least one of the driver lines with a first one of the devices therebetween, and each test structure is connected to at least one of the receiver lines with a second one of the devices therebetween, so that each of the test structures can be individually addressed for testing using the driver lines and receiver lines.
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Specification