Memory controller with multi-protocol interface

• US 20090037641A1
• Filed: 07/31/2007
• Published: 02/05/2009
• Est. Priority Date: 07/31/2007
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Bresniker, Kirk M.
• Granted Patent: US 8,347,005 B2
• Time in Patent Office: Days
• US Class Current: 711/100
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types

Abstract

A multi-protocol memory controller includes one or more memory channel controllers. Each of the memory channel controllers coupled to a single channel of DIMM, where the DIMM in each single channel operate according to a specific protocol. A protocol engine is coupled to the memory channel controllers. The protocol engine is configurable to accommodate one or more of the specific protocols. Finally, a system interface is coupled to the protocol engine and is configurable to provide electrical power and signaling appropriate for the specific protocols.

Claims

1. A multi-protocol memory controller, comprising:

one or more memory channel controllers, each of the memory channel controllers coupled to a single channel of DIMM, wherein the DIMM in each single channel operate according to a specific protocol;

a protocol engine coupled to the memory channel controllers, wherein the protocol engine is configurable to accommodate one or more of the specific protocols; and

a system interface coupled to the protocol engine and configurable to provide electrical power and signaling appropriate for the specific protocols.

2. The controller of claim 1, wherein the memory channels comprise one or more first memory channels having memory devices operable according to a first protocol and one or more second memory channels operable according to a second protocol.

3. The controller of claim 1, wherein the protocols include fully buffered DIMM protocol, PCI-E protocol, Ethernet with iWARP/RDMA protocol, cHT protocol, and CSI cache coherency protocol.

4. The controller of claim 1, wherein the DIMM are DDR3 DIMM.

5. The controller of claim 1, wherein the system interface comprises:

TX and RX deserializer skew buffers; and

LVDS drivers.

6. The controller of claim 1, wherein the protocol engine is pre-loaded with memory device protocols.

7. The controller of claim 1, wherein the protocol engine is loaded with appropriate protocols upon configuration of a corresponding host system and memory sub-system.

8. The controller of claim 1, wherein the memory channel controllers provide a very low power hibernation mode.

9. The controller of claim 1, wherein the memory channel controllers, the protocol engine, and the system interface, are coupled to a configuration management module, and wherein the configuration management module is operable to configure the protocol engine and the system interface.

10. The controller of claim 1, wherein the controller provides coherent memory control and non-coherent input/output.

11. A multi-protocol memory controller for use with a host computing system, comprising:

means for controlling operation of one or more channels of memory the one or more memory channels comprising one or more different types of memory devices; and

means for supplying signaling and electrical power from the host system to the memory devices.

12. The multi-protocol memory controller of claim 11, wherein the controlling means, comprises:

a memory channel controller for each of the one or more memory channels;

a protocol engine coupled to the one or more memory channel controllers, wherein the protocol engine is configurable to accommodate one or more specific memory device protocols; and

means for selecting protocols appropriate to the memory devices.

13. The multi-protocol memory controller of claim 12, wherein the means for selecting protocols comprises a configuration management module, and wherein the configuration management module provides for one or more of automatic selection of a protocol based on identification of a memory type and user selection of the protocol.

14. The multi-protocol memory controller of claim 11, wherein the means for supplying comprises wherein the system interface comprises:

TX and RX deserializer skew buffers; and

LVDS drivers.

15. The multi-protocol memory controller of claim 11, further comprising means for placing the multi-protocol memory controller and the memory devices in a low=power mode.

16. A multi-protocol memory controller coupled to one or more channels of memory devices, all the memory devices in a specific channel operating according to a same protocol, the memory controller, comprising:

a memory channel controller coupled to each of the one or more channels of memory devices;

a protocol engine configurable to operate run a plurality of protocols; and

means for selecting one or more of the plurality of protocols depending on types of the memory devices in the one or more channels.

17. The multi-protocol memory controller of claim 16, further comprising an interface to provide signaling and power from one or more devices external to the memory expansion blade.

18. The multi-protocol memory controller of claim 16, wherein the channels of memory comprise one or more first memory channels having memory devices operable according to a first protocol and one or more second memory channels operable according to a second protocol.

19. The multi-protocol memory controller of claim 16, wherein the protocols include fully buffered DIMM protocol, Infiniband, PCI-E protocol, Ethernet with iWARP/RDMA protocol, cHT protocol, and CSI cache coherency protocol.

20. The multi-protocol memory controller of claim 16, further comprising a low power sleep mode useable to minimize power consumption.