Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules

• US 20090037652A1
• Filed: 10/15/2008
• Published: 02/05/2009
• Est. Priority Date: 12/02/2003
• Status: Active Grant

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Ma, Abraham C., Lee, Charles C., Yu, Frank
• Granted Patent: US 8,037,234 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0632 by initialisation or re-initialisation of storage systems
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells

Abstract

A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.

Claims

1. A multi-level flash device comprising:

a smart storage switch which comprises;

an upstream interface to a host for receiving host commands to access non-volatile memory (NVM) and for receiving host data and a host address;

a smart storage transaction manager that manages transactions from the host;

a virtual storage processor that maps the host address to an assigned flash module to generate a logical block address (LBA), the virtual storage processor performing a first level of mapping;

a virtual storage bridge between the smart storage transaction manager and a LBA bus;

a NVM controller, coupled to the LBA bus to receive the LBA generated by the virtual storage processor and the host data from the virtual storage bridge;

a second-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA);

a plurality of flash modules that include the assigned flash module, wherein a flash module comprises;

raw-NAND flash memory chips, coupled to the NVM controller, for storing the host data at a block location identified by the PBA generated by the second-level mapper in the NVM controller;

whereby address mapping is performed at two levels to access the raw-NAND flash memory chips.

2. The multi-level flash device of claim 1 wherein the NVM controller is integrated on the flash module, wherein the flash module further comprises the NVM controller.

3. The multi-level flash device of claim 2 further comprising:

a local clock source, within each of the plurality of flash modules, for generating local clocks for clocking the NVM controllers and interfaces to the raw-NAND flash memory chips,

wherein local clocks are generated within each of the plurality of flash modules.

4. The multi-level flash device of claim 1 wherein the flash module is physically mounted to a host motherboard through a connector and socket, by direct solder attachment, or embedded within the host motherboard.

5. The multi-level flash device of claim 1 wherein the NVM controller is integrated with the smart storage switch.

6. The multi-level flash device of claim 1 wherein the smart storage switch further comprises:

a data striping unit that divides the host data into data segments that are assigned to different ones of the plurality of flash modules;

a parity generator for generating error detecting code for the host data, the error correcting code being stored with the host data,

whereby error detection code is added at a top level by the smart storage switch.

7. The multi-level flash device of claim 1 further comprising:

a volatile memory buffer for temporarily storing the host data in a volatile memory that loses data when power is disconnected;

wherein the raw-NAND flash memory chips in the plurality of flash module are non-volatile memory that retain data when power is disconnected;

wherein the smart storage switch further comprises;

a virtual buffer bridge, coupled between the smart storage transaction manager and the volatile memory buffer.

8. The multi-level flash device of claim 7 further comprising:

a sector data buffer, in the volatile memory buffer, for temporarily caching the host data, the sector data buffer having L locations for storing the host data;

a Q-R pointer table, in the volatile memory buffer, for storing a quotient Q and a remainder R generated by division of a host address by L;

wherein Q, R, and L are whole numbers;

wherein R identifies one of the L locations in the sector data buffer.

9. The multi-level flash device of claim 8 further comprising:

a command queue, in the volatile memory buffer, for storing entries for commands received from the host that have not yet written data to the raw-NAND flash memory chips.

10. The multi-level flash device of claim 9 further comprising:

a data-type field in the command queue, the data-type field for prioritizing commands in the command queue, wherein the data-type field indicates an immediate cast-out operation of old host data in the sector data buffer that has a higher priority that other writes to flash memory;

a cross-boundary flag in the command queue, the cross-boundary flag indicating when a host command transfers data to multiple locations in the sector data buffer that include a last location identified by a largest remainder R and a first location identified by a smallest remainder R.

11. A solid-state disk comprising:

volatile memory buffer means for temporarily storing host data in a volatile memory that loses data when power is disconnected;

smart storage switch means for switching host commands to a plurality of downstream devices, the smart storage switch means comprising;

upstream interface means, coupled to a host, for receiving host commands to access flash memory and for receiving host data and a host address;

smart storage transaction manager means for managing transactions from the host;

virtual storage processor means for translating the host address to an assigned flash module to generate a logical block address (LBA), the virtual storage processor means performing a first level of mapping;

virtual storage bridge means for transferring host data and the LBA between the smart storage transaction manager means and a LBA bus;

data striping means for dividing the host data into data segments that are assigned to different ones of the plurality of flash modules;

a plurality of flash modules that include the assigned flash module, wherein a flash module comprises;

lower-level controller means for controlling flash operations, coupled to the LBA bus to receive the LBA generated by the virtual storage processor means and the host data from the virtual storage bridge means;

second-level map means, in the lower-level controller means, for mapping the LBA to a physical block address (PBA); and

raw-NAND flash memory chips, coupled to the lower-level controller means, for storing the host data at a block location identified by the PBA generated by the second-level map means in the lower-level controller means;

wherein the raw-NAND flash memory chips in the plurality of flash modules are non-volatile memory that retain data when power is disconnected,

whereby address mapping is performed at two levels to access the raw-NAND flash memory chips.

12. The solid-state disk of claim 11 further comprising:

sector data buffer means, in the volatile memory buffer means, for storing host data, the sector data buffer means having L locations for storing host data;

command queue means, in the volatile memory buffer means, for storing entries for commands received from the host that have not yet written data to the raw-NAND flash memory chips; and

Q-R pointer table means, in the volatile memory buffer means, for storing a quotient Q and a remainder R generated by division of a host address by L;

wherein Q, R, and L are whole numbers;

wherein R identifies one of the L locations in the sector data buffer means.

13. The solid-state disk of claim 11 wherein the raw-NAND flash memory chips comprise two flash die that are stacked together and accessible by interleaving, and wherein each of the two flash die comprises two planes that are accessible by interleaving;

wherein a size of a data segment is equal to four pages per channel, and each channel has one of the plurality of flash modules, whereby the host data is striped with a depth to match the plurality of flash modules.

14. The solid-state disk of claim 13 wherein a stripe depth is equal to N times a stripe size, wherein N is a whole number of the plurality of flash modules, and wherein the stripe size is equal to a number of pages that can be simultaneously written into one of the plurality of flash modules.

15. The solid-state disk of claim 11 wherein the flash module comprises a flash module that is physically mounted to a host motherboard through a connector and socket, by direct solder attachment, or embedded within the host motherboard.

16. A striping non-volatile-memory (NVM) system comprising:

an upstream interface to a host that generates host data and host commands in a host sequence of commands;

a smart storage transaction manager, coupled to the upstream interface, for re-ordering the host commands from the host sequence into a reordered sequence of operations;

a plurality of NVM modules each having a plurality of NVM memory blocks for storing the host data in non-volatile solid-state memory that retains data when power is disconnected;

a virtual storage processor that assigns host commands to an assigned device in the plurality of NVM modules, the virtual storage processor also storing attributes obtained from each of the plurality of NVM modules, the attributes including memory capacities, wherein the virtual storage processor reports an aggregate sum of the memory capacities to the host;

a data striping unit for segmenting host data into data segments stored on several of the plurality of NVM modules;

a virtual storage bridge, coupled between the smart storage transaction manager and the plurality of NVM modules;

a lower-level controller for each of the plurality of NVM modules, the lower-level controller comprising;

a remapping unit for converting logical addresses received from the virtual storage bridge into physical addresses for accessing the plurality of NVM memory blocks in the NVM module;

whereby high-level data striping is performed before the host data is sent to the plurality of NVM modules.

17. The striping non-volatile-memory system of claim 16 further comprising:

a truncation process, activated on power-up, for determining a smallest size of the plurality of NVM modules, and for setting a size of all NVM modules in the plurality of NVM modules to the smallest size;

wherein the NVM memory blocks comprises a flash memory, a phase-change memory (PCM), ferroelectric random-access memory (FRAM), Magnetoresistive RAM (MRAM), Memristor, PRAM, SONOS, Resistive RAM (RRAM), Racetrack memory, or nano RAM (NRAM).

18. The striping non-volatile-memory system of claim 16 further comprising:

a dynamic-random-access memory (DRAM) buffer for temporarily storing the host data;

a virtual buffer bridge between the DRAM buffer and the smart storage transaction manager,

a sector data buffer, in the DRAM buffer, for temporarily caching the host data, the sector data buffer having L locations for storing the host data;

a Q-R pointer table, in the DRAM buffer, for storing a quotient Q and a remainder R generated by division of a host address by L;

wherein Q, R, and L are whole numbers;

wherein R identifies one of the L locations in the sector data buffer.

19. The striping non-volatile-memory system of claim 18 further comprising:

a command queue, in the DRAM buffer, for storing entries for commands received from the host that have not yet written data to the NVM memory blocks.

20. A physical-block-address (PBA) flash module comprising:

a substrate having wiring traces printed thereon, the wiring traces for conducting signals;

a plurality of metal contact pads along a first edge of the substrate, the plurality of contact pads for mating with a memory module socket on a board;

a plurality of non-volatile memory chips mounted on the substrate for storing host data from a host on the board;

wherein the plurality of non-volatile memory chips retain data when power is disconnected to the flash module; and

a physical-block-address PBA bus formed by wiring traces on the substrate that connect to the plurality of metal contact pads;

wherein the PBA flash module connects the plurality of non-volatile memory chips to the board through the PBA bus.

21. A logical-block-address (LBA) flash module comprising:

a substrate having wiring traces printed thereon, the wiring traces for conducting signals;

a plurality of metal contact pads along a first edge of the substrate, the plurality of contact pads for mating with a memory module socket on a board;

a plurality of non-volatile memory chips mounted on the substrate for storing host data from a host on the board;

wherein the plurality of non-volatile memory chips retain data when power is disconnected to the flash module;

a logical-block-address LBA bus formed by wiring traces on the substrate that connect to the plurality of metal contact pads;

a non-volatile-memory (NVM) controller, mounted on the substrate, coupled to the LBA bus to receive a LBA from the board through the plurality of metal contact pads;

a second-level mapper, in the NVM controller, that maps the LBA to a physical block address (PBA); and

a PBA bus formed from an internal subset of the wiring traces on the substrate, the internal subset of wiring traces not connecting to the plurality of metal pads;

wherein the plurality of non-volatile memory chips are coupled by the PBA bus to the NVM controller;

wherein the plurality of non-volatile memory chips store host data sent over the plurality of metal pads at a block location identified by the PBA generated by the second-level mapper in the NVM controller;

wherein the flash module connects the plurality of non-volatile memory chips to the board through the PBA bus, the NVM controller, and the LBA bus.