SYSTEM AND METHOD OF LOAD-STORE FORWARDING

• US 20090037697A1
• Filed: 08/01/2007
• Published: 02/05/2009
• Est. Priority Date: 08/01/2007
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lauterbach, Gary, Ramani, Krishnan
• Granted Patent: US 7,822,951 B2
• Time in Patent Office: Days
• US Class Current: 712/214
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency

Abstract

A system and method for data forwarding from a store instruction to a load instruction during out-of-order execution, when the load instruction address matches against multiple older uncommitted store addresses or if the forwarding fails during the first pass due to any other reason. In a first pass, the youngest store instruction in program order of all store instructions older than a load instruction is found and an indication to the store buffer entry holding information of the youngest store instruction is recorded. In a second pass, the recorded indication is used to index the store buffer and the store bypass data is forwarded to the load instruction. Simultaneously, it is verified if no new store, younger than the previously identified store and older than the load has not been issued due to out-of-order execution.

Claims

1. A method comprising:

storing information of uncommitted load instructions in a first plurality of entries;

storing information of uncommitted store instructions in a second plurality of entries;

conveying first information of a first load instruction to each entry of the second plurality of entries;

storing a set retry bit and a store index corresponding to a chosen store instruction in a first entry of the first plurality of entries corresponding to the first load instruction; and

conveying bypass data from an entry of the second plurality of entries selected by the store index to the first load instruction.

2. The method as recited in claim 1, further comprising:

conveying the first information in a first time period;

storing the set retry bit and the index in the first time period; and

conveying bypass data in a second time period following the first time period.

3. The method as recited in claim 2, further comprising:

in response to the conveyed first information, selecting a third plurality of entries among the second plurality of entries in the first time period;

selecting the chosen store instruction from the third plurality of entries in the first time period; and

conveying the store index from the first entry to the second plurality of entries in the second time period.

4. The method as recited in claim 3, further comprising the chosen store instruction comprises a youngest store instruction of all store instructions older than the first load instruction in program order.

5. The method as recited in claim 4, further comprising:

the first information comprises an address of the first load instruction; and

the first time period is a single clock cycle.

6. The method as recited in claim 5, further comprising selecting the third plurality of entries by determining a match between the first information and an address of each entry of the second plurality of entries.

7. A computer system comprising:

a processor comprising a load-store unit; and

a memory coupled to the processor;

wherein the processor is configured to issue load and store operations to the load-store unit;

wherein the load-store unit is configured to;

store information of uncommitted load instructions in a first plurality of entries;

store information of uncommitted store instructions in a second plurality of entries;

convey first information of a first load instruction to each entry of the second plurality of entries;

store a set retry bit and a store index, corresponding to a chosen store instruction, in a first entry of the first plurality of entries corresponding to the first load instruction; and

convey bypass data from an entry of the second plurality of entries selected by the store index to the first load instruction.

8. The system as recited in claim 7, wherein the load-store unit is further configured to:

convey the first information in a first time period;

store the set retry bit and the index in the first time period; and

convey bypass data in a second time period following the first time period.

9. The system as recited in claim 8, wherein the load-store unit further configured to:

in response to the conveyed first information, select a third plurality of entries among the second plurality of entries in the first time period;

select the chosen store instruction from the third plurality of entries in the first time period; and

convey the store index from the first entry to the second plurality of entries in the second time period.

10. The system as recited in claim 9, wherein the chosen store instruction comprises a youngest store instruction of all store instructions older than the first load instruction in program order.

11. The system as recited in claim 10, further comprising:

the first information comprises an address of the first load instruction; and

the first time period is a single clock cycle.

12. The system as recited in claim 11, wherein the load-store unit is further configured to select the third plurality of entries by determining a match between the first information and an address of each entry of the second plurality of entries.

13. A load-store unit comprising:

a load buffer comprising a first plurality of entries, wherein an entry stores information of an uncommitted load instruction;

a store buffer comprising a second plurality of entries, wherein an entry stores information of an uncommitted store instruction; and

a priority encoder;

wherein the load buffer is configured to convey first information of a first load instruction to each entry of the store buffer;

wherein the load buffer is configured to store a set retry bit and a store index, corresponding to a chosen store instruction, in a first entry corresponding to the first load instruction, wherein the set retry bit and the store index are conveyed by the priority encoder; and

wherein the store buffer is configured to convey bypass data selected by the store index to the first load instruction.

14. The load-store unit as recited in claim 13, wherein the load-store unit is further configured to:

convey the first information in a first time period;

store the set retry bit and the index in the first time period; and

convey bypass data in a second time period following the first time period.

15. The load-store unit as recited in claim 14, wherein the load-store unit further configured to:

in response to the conveyed first information, select a third plurality of entries among the second plurality of entries in the first time period;

convey the third plurality of entries from the store buffer to the priority encoder in the first time period;

select via the priority encoder a chosen store instruction from the third plurality of entries in the first time period; and

convey the store index from the first entry to the store buffer in the second time period.

16. The load-store unit as recited in claim 15, wherein the chosen store instruction comprises a youngest store instruction of all store instructions older than the first load instruction in program order.

17. The load-store unit as recited in claim 16 further comprising:

the first information comprises an address of the first load instruction; and

the first time period is a single clock cycle.

18. The load-store unit as recited in claim 17, wherein the store buffer is further configured to select the third plurality of entries by determining a match between the first information and an address of each entry of the second plurality of entries.

19. The load-store unit as recited in claim 18, wherein an entry of the first plurality of entries is further configured to store one or more of a valid bit, a retry bit, a store buffer index, and an indication of age and an address of an uncommitted load instruction.

20. The load-store unit as recited in claim 19, wherein the entry of the second plurality of entries is further configured to store one or more of a valid bit, a store buffer index, and an indication of age, an address, and data of an uncommitted store instruction.