Method and apparatus for unifying self-test with scan-test during prototype debug and production test

• US 20090037786A1
• Filed: 09/30/2008
• Published: 02/05/2009
• Est. Priority Date: 04/09/2002
• Status: Active Grant

• Current Assignee: Syntest Technologies Incorporated
• Original Assignee: Syntest Technologies Incorporated
• Inventors: Chang, Ming-Tung, Wang, Hsin-Po, Wang, Laung-Terng, Wen, Xiaoqing, Hsu, Chi-Chan, Kao, Shih-Chia, Lin, Meng-Chyi, Lin, Shyh-Horng, Abdel-Hafez, Khader S., Hsu, Po-Ching
• Granted Patent: US 7,747,920 B2
• Time in Patent Office: Days
• US Class Current: 714/731
• CPC Class Codes: G01R 31/318586 with partial scan or non-scannable parts
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552
• CPC Class Codes: G06F 11/27 Built-in tests

Abstract

A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

Claims

1-24. -24. (canceled)

25. A method for testing or diagnosing a plurality of clock domains in a scan-based integrated circuit in selected self-test or scan-test mode, the scan-based integrated circuit having a global scan enable (GSE) signal and a test clock, each domain having a system clock, a scan clock, a scan enable (SE) signal, and a plurality of scan cells connected to form one or more scan chains;

said method comprising the steps of;

(a) concurrently shifting a test stimulus into all said scan chains of each said clock domain by clocking said scan clock controlling each said clock domain at a shift clock speed, selectively derived from said test clock or said system clock of said clock domain, for a predetermined number of shift clock cycles, when said global scan enable (GSE) signal is set to logic value ‘

1’

during the shift-in operation;

(b) capturing a test response into said scan chains of each said clock domain in an ordered sequence by clocking said scan clock controlling each said clock domain at a selected capture clock speed, selectively derived from said test clock or said system clock of said clock domain, for a predetermined number of capture clock cycles, when said global scan enable (GSE) signal is set to logic value ‘

0’

during the capture operation; and

(c) concurrently shifting said test response out of all said scan chains of each said clock domain for comparison or compaction by clocking said scan clock controlling each said clock domain at a shift clock speed, selectively derived from said test clock or said system clock of said clock domain, for said predetermined number of shift clock cycles, when said global scan enable (GSE) signal is set to logic value ‘

1’

during the shift-out operation.

26. The method of claim 25, wherein said shift-in operation and said shift-out operation can occur concurrently.

27. The method of claim 25, wherein said scan enable (SE) signal controlling one said clock domain is further derived from said global scan enable (GSE) signal during said capture operation, when said clock domain is to be tested or diagnosed with selected stuck-type faults;

wherein said stuck-type faults further include stuck-at faults, bridging faults, and IDDQ (IDD quiescent current) faults.

28. The method of claim 27, wherein said scan enable (SE) signal controlling one said clock domain is set to logic value ‘

0’

throughout all said capture clock cycles during said capture operation.

29. The method of claim 25, wherein said scan enable (SE) signal controlling one said clock domain is further derived from said global scan enable (GSE) signal during said capture operation, when said clock domain is to be tested or diagnosed with selected non-stuck-type faults;

wherein said non-stuck-type faults further include transition faults using capture launch, path-delay faults using capture launch, and multiple-cycle delay faults using capture launch.

30. The method of claim 29, wherein said scan enable (SE) signal controlling one said clock domain is set to logic value ‘

0’

throughout all said capture clock cycles during said capture operation.

31. The method of claim 25, wherein said scan enable (SE) signal controlling one said clock domain is further derived from said global scan enable (GSE) signal, said test clock, and said system clock of said clock domain, when said clock domain is to be tested or diagnosed with selected non-stuck-type faults;

wherein said non-stuck-type faults further include transition faults using last-shift launch, path-delay faults using last-shift launch, and multiple-cycle delay faults using last-shift launch.

32. The method of claim 31, wherein said scan enable (SE) signal controlling one said clock domain is set to logic value ‘

1’

for the first said capture clock cycle and ‘

0’

for the second and thereafter said capture clock cycles during said capture operation.

33. The method of claim 25, wherein said capturing a test response into said scan chains of each said clock domain in an ordered sequence by clocking said scan clock controlling each said clock domain at a selected capture clock speed further comprises performing said capture operation concurrently on selected clock domains which do not have any logic block crossing each other or any unpredictable data signal traversing from one said selected clock domain to another said selected clock domain, in said selected self-test mode or said selected scan-test mode.

34. The method of claim 25, wherein said capturing a test response into said scan chains of each said clock domain in an ordered sequence by clocking said scan clock controlling each said clock domain at a selected capture clock speed further comprises applying said scan clocks in a selected order for detecting or locating additional faults in said scan-based integrated circuit.

35. The method of claim 25, wherein said capturing a test response into said scan chains of each said clock domain in an ordered sequence by clocking said scan clock controlling each said clock domain at a selected capture clock speed further comprises applying another ordered sequence of scan clocks selectively longer or shorter than said ordered sequence of scan clocks for detecting or locating additional faults in said scan-based integrated circuit.

36. The method of claim 25, wherein said capturing a test response into said scan chains of each said clock domain in an ordered sequence by clocking said scan clock controlling each said clock domain at a selected capture clock speed further comprises disabling one or more said scan clocks to facilitate fault detection or fault diagnosis.

37. The method of claim 25, wherein said capturing a test response into said scan chains of each said clock domain in an ordered sequence by clocking said scan clock controlling each said clock domain at a selected capture clock speed further comprises selectively operating said scan clock at a selected clock speed derived from said test clock or said system clock of said clock domain for detecting or locating stuck-at faults within said clock domain controlled by said scan clock.

38. The method of claim 25, wherein said capturing a test response into said scan chains of each said clock domain in an ordered sequence by clocking said scan clock controlling each said clock domain at a selected capture clock speed further comprises selectively operating said scan clock at its rated clock speed (at-speed) derived from said system clock of said clock domain for detecting or locating delay faults within said clock domain controlled by said scan clock.

39. The method of claim 25, wherein said capturing a test response into said scan chains of each said clock domain in an ordered sequence by clocking said scan clock controlling each said clock domain at a selected capture clock speed further comprises selectively reducing said scan clock speed derived from said system clock of said clock domain to the level where delay faults associated with all multiple-cycle paths of equal cycle latency within said clock domain are tested at a predetermined rated clock speed (at-speed).

40. The method of claim 25, wherein said capturing a test response into said scan chains of each said clock domain in an ordered sequence by clocking said scan clock controlling each said clock domain at a selected capture clock speed further comprises selectively operating two said scan clocks at selected clock speeds for detecting or locating stuck-at faults crossing two said clock domains.

41. The method of claim 25, wherein said capturing a test response into said scan chains of each said clock domain in an ordered sequence by clocking said scan clock controlling each said clock domain at a selected capture clock speed further comprises selectively adjusting the relative clock delay of two said scan clocks operating at selected clock speeds for detecting or locating delay faults crossing two said clock domains.

42. The method of claim 25, wherein said capturing a test response into said scan chains of each said clock domain in an ordered sequence by clocking said scan clock controlling each said clock domain at a selected capture clock speed further comprises selectively adjusting the relative clock delay of two said scan clocks to the level where delay faults associated with all multiple-cycle paths of equal cycle latency crossing two said clock domains are tested at a predetermined rated clock speed.

43. The method of claim 25, wherein said global scan enable (GSE) signal can be selectively generated within said scan-based integrated circuit or controlled externally.

44. The method of claim 25, wherein said test clock is derived from an external test clock.

45. The method of claim 44, wherein said external test clock is further derived from one said system clock controlling one said clock domain within said scan-based integrated circuit.

46. The method of claim 25, further including a TAP (Test access port) controller in said selected self-test mode or said selected scan-test mode;

wherein said TAP controller is constructed according to a selected Boundary-scan Standard which includes a test access port (TAP) comprising TDI (Test data in), TDO (Test data out), TCK (Test clock), TMS (Test mode select), and selectively TRSTB (Test reset).

47. The method of claim 46, wherein said TAP controller further comprises means for generating said global scan enable (GSE) signal within said scan-based integrated circuit.

48. The method of claim 46, wherein said TAP controller further comprises means for generating said test clock within said scan-based integrated circuit;

wherein said test clock is selectively derived from said TCK or one said system clock controlling one said clock domain within said scan-based integrated circuit.