METHOD FOR SORTING INTEGRATED CIRCUIT DEVICES

• US 20090038997A1
• Filed: 10/09/2008
• Published: 02/12/2009
• Est. Priority Date: 01/17/1997
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Beffa, Raymond J.
• Granted Patent: US 7,875,821 B2
• Time in Patent Office: Days
• US Class Current: 209/573
• CPC Class Codes: B07C 5/3412 according to a code applied to the object which indicates a property of the object, e.g. quality class, contents or incorrect indication sorting according to size measured by light-responsive means B07C5/10; sorting according to optical properties B07C5/342; for packages B65D79/02; for information carriers G06K7/00
• CPC Class Codes: B07C 5/344 according to electric or electromagnetic properties sorting according to size measured electrically or electronically B07C5/08; material testing by magnetic means G01N24/00, G01N27/00, by electrical means G01N27/00; electrical measuring devices in general G01R; coin testing G07D5/00
• CPC Class Codes: G01R 31/2851 Testing of integrated circuits [IC] G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, including automatically reading the ID code of each of the IC devices and sorting the IC devices in accordance with their automatically read ID codes, is disclosed.

Claims

1. A method for sorting integrated circuit (IC) devices comprising:

programming each of the IC devices with a respective identification (ID) code;

testing the IC devices using a first standard, wherein test data generated during the testing is associated with the IDs;

separating those of the IC devices that do not pass the first standard;

automatically reading the ID code of at least one of the IC devices that did not pass the first standard;

accessing the test data associated with the automatically read ID code;

comparing the accessed test data with a second standard, wherein the second standard is relaxed in comparison to the first standard, to determine if the IC device corresponding to the automatically read ID code passes the second standard without retesting that IC device.

2. The method of claim 1, wherein accessing the test data associated with each of the automatically read ID codes comprises accessing the test data indicating each of the IC devices is from one of a control group, a Special Work Request (SWR) group, and a deviation lot, wherein the step of sorting the IC devices in accordance with the accessed test data comprises sorting the IC devices in accordance with their being from one of a control group, an SWR group, and a deviation lot.

3. The method of claim 1, wherein accessing the test data associated with each of the automatically read ID codes comprises accessing the test data indicating at least one of the IC devices should undergo different testing than the other IC devices, wherein the step of sorting the IC devices in accordance with the accessed test data comprises sorting the IC devices in accordance with the testing it is indicated they should undergo.

4. The method of claim 1, wherein each of the IC devices has an associated lot ID, wherein the step of accessing the test data associated with each of the automatically read ID codes comprises accessing the test data associated with the lot ID of the IC device associated with each of the automatically read ID codes.

5. The method of claim 1, further comprising fabricating a plurality of ICs on each of a plurality of semiconductor wafers including fabricating ICs of different types selected from a group comprising Dynamic Random Access Memory (DRAM) ICs, Static Random Access Memory (SRAM) ICs, Synchronous DRAM (SDRAM) ICs, and processor ICs.

6. The method of claim 1, wherein testing each of the IC devices comprises the test steps of hot pre-grade, burn-in, hot final, cold final, and scanning.

7. The method of claim 1, wherein automatically reading comprises automatically reading an ID code from the IC in each of the IC devices occurs before the step of testing each of the IC devices.

8. A method for sorting integrated circuit IC devices having their ID automatically read, information associated with the ID accessed, and the information of each IC device compared comprising:

testing the integrated circuit devices using a first standard, wherein test data generated during the testing is associated with the IDs;

separating those of the integrated circuit devices that do not pass the first standard;

comparing the accessed test data with a second standard, wherein the second standard is relaxed in comparison to the first standard, to determine if the IC device corresponding to the automatically read ID passes the second standard without retesting that IC device.

9. The method of claim 8, further comprising automatically accessing data indicating each of the IC devices is from one of a control group, a Special Work Request (SWR) group, and a deviation lot, and sorting the IC devices in accordance with their being from one of a control group, an SWR group, and a deviation lot.

10. The method of claim 8, further comprising accessing data indicating at least one of the IC devices should undergo different testing than the other IC devices, and sorting the IC devices in accordance with the testing it is indicated they should undergo.

11. The method of claim 8, wherein each of the IC devices has an associated lot ID, and accessing data associated with the lot ID of the IC device associated with each of the automatically read ID codes.

12. The method of claim 8, further comprising fabricating a plurality of ICs on each of a plurality of semiconductor wafers including fabricating ICs of different types selected from a group comprising Dynamic Random Access Memory (DRAM) ICs, Static Random Access Memory (SRAM) ICs, Synchronous DRAM (SDRAM) ICs, and processor ICs.

13. The method of claim 8, wherein testing each of the IC devices comprises the test steps of hot pre-grade, burn-in, hot final, cold final, and scanning.

14. The method of claim 8, further comprising automatically reading the ID code from an IC in each of the IC devices occurs before the step of testing each of the IC devices.

15. A method for sorting Integrated circuit devices after automatically reading their ID, information associated with the ID accessed, comprising:

testing the Integrated circuit devices using a first standard, wherein test data generated during the testing is associated with the IDs;

separating those of the Integrated circuit devices that do not pass the first standard;

comparing the accessed test data with a second standard, wherein the second standard is relaxed in comparison to the first standard, to determine if the IC device corresponding to the read ID passes the second standard without retesting that IC device.

16. The method of claim 15, further comprising in connection with automatically accessing data indicating each of the IC devices is from one of a control group, a Special Work Request (SWR) group, and a deviation lot, and in connection with sorting the IC devices in accordance with the accessed data comprises sorting the IC devices in accordance with their being from one of a control group, an SWR group, and a deviation lot.

17. The method of claim 15, further comprising in connection with accessing data indicating at least one of the IC devices should undergo different testing than the other IC devices, and in connection with sorting the IC devices in accordance with the accessed data comprises sorting the IC devices in accordance with the testing it is indicated they should undergo.

18. The method of claim 15, wherein each of the IC devices has an associated lot ID, and in connection with accessing data associated with the lot ID of the IC device associating data with each of the automatically read ID codes.

19. The method of claim 15, further comprising in connection with fabricating a plurality of ICs on each of a plurality of semiconductor wafers includes fabricating ICs of different types selected from a group comprising Dynamic Random Access Memory (DRAM) ICs, Static Random Access Memory (SRAM) ICs, Synchronous DRAM (SDRAM) ICs, and processor ICs.

20. The method of claim 15, wherein in connection with testing each of the IC devices includes test procedures of hot pre-grade, burn-in, hot final, cold final, and scanning.

21. The method of claim 15, further comprising in connection with automatically reading the ID code from the IC in each of the IC devices occurring before the step of testing each of the IC devices.